riscv/rocket-chip
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Don't report exceptions as valid instructions in the printed log

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This commit is contained in:
Andrew Waterman 2017-09-27 16:29:42 -07:00
parent 31c5246446
commit 9eaf50762e
1 changed files with 3 additions and 2 deletions
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5
src/main/scala/rocket/RocketCore.scala
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@ -671,7 +671,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
val wxd = wb_ctrl.wxd val wxd = wb_ctrl.wxd
val has_data = wb_wen && !wb_set_sboard val has_data = wb_wen && !wb_set_sboard
when (t.valid) { when (t.valid && !t.exception) {
when (wfd) { when (wfd) {
printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+UInt(32)) printf ("%d 0x%x (0x%x) f%d p%d 0xXXXXXXXXXXXXXXXX\n", t.priv, t.iaddr, t.insn, rd, rd+UInt(32))
} }
@ -692,7 +692,8 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
} }
else { else {
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n", printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
io.hartid, csr.io.time(31,0), csr.io.trace(0).valid, csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0), io.hartid, csr.io.time(31,0), csr.io.trace(0).valid && !csr.io.trace(0).exception,
csr.io.trace(0).iaddr(vaddrBitsExtended-1, 0),
Mux(rf_wen && !(wb_set_sboard && wb_wen), rf_waddr, UInt(0)), rf_wdata, rf_wen, Mux(rf_wen && !(wb_set_sboard && wb_wen), rf_waddr, UInt(0)), rf_wdata, rf_wen,
wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))), wb_reg_inst(19,15), Reg(next=Reg(next=ex_rs(0))),
wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))), wb_reg_inst(24,20), Reg(next=Reg(next=ex_rs(1))),