riscv/rocket-chip
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rocket: clarify intent of boundaryBuffers and move to RocketTile

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This commit is contained in:
Wesley W. Terpstra 2017-10-26 13:52:34 -07:00
parent e76e0f6dce
commit 9e33ccdb05
2 changed files with 30 additions and 15 deletions
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6
src/main/scala/coreplex/RocketCoreplex.scala
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@ -57,8 +57,7 @@ case class TileSlavePortParams(
case class RocketCrossingParams(
crossingType: CoreplexClockCrossing = SynchronousCrossing(),
master: TileMasterPortParams = TileMasterPortParams(),
slave: TileSlavePortParams = TileSlavePortParams(),
boundaryBuffers: Boolean = false) {
slave: TileSlavePortParams = TileSlavePortParams()) {
def knownRatio: Option[Int] = crossingType match {
case RationalCrossing(_) => Some(2)
case _ => None
@ -92,8 +91,7 @@ trait HasRocketTiles extends HasTiles
// in the global Parameters about the specific tile being built now
val wrapper = LazyModule(new RocketTileWrapper(
params = tp,
crossing = crossing.crossingType,
boundaryBuffers = crossing.boundaryBuffers
crossing = crossing.crossingType
)(p.alterPartial {
case TileKey => tp
case BuildRoCC => tp.rocc

37
src/main/scala/tile/RocketTile.scala
View File

@ -22,7 +22,9 @@ case class RocketTileParams(
trace: Boolean = false,
hcfOnUncorrectable: Boolean = false,
name: Option[String] = Some("tile"),
hartid: Int = 0) extends TileParams {
hartid: Int = 0,
boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
) extends TileParams {
require(icache.isDefined)
require(dcache.isDefined)
}
@ -189,23 +191,38 @@ class RocketTileWrapperBundle[+L <: RocketTileWrapper](_outer: L) extends BaseTi
class RocketTileWrapper(
params: RocketTileParams,
val crossing: CoreplexClockCrossing,
val boundaryBuffers: Boolean = false)
val crossing: CoreplexClockCrossing)
(implicit p: Parameters) extends BaseTile(params) with HasCrossing {
val rocket = LazyModule(new RocketTile(params))
// The buffers needed to cut feed-through paths are microarchitecture specific, so belong here
val masterBuffer = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
val masterNode: TLOutwardNode = if (boundaryBuffers) {
val masterNode: TLOutwardNode = crossing match {
case _: AsynchronousCrossing => rocket.masterNode
case SynchronousCrossing(b) =>
require (!params.boundaryBuffers || (b.depth >= 1 && !b.flow && !b.pipe), "Buffer misconfiguration creates feed-through paths")
rocket.masterNode
case RationalCrossing(dir) =>
require (dir != SlowToFast, "Misconfiguration? Core slower than fabric")
if (params.boundaryBuffers) {
masterBuffer.node :=* rocket.masterNode
masterBuffer.node
} else { rocket.masterNode }
} else {
rocket.masterNode
}
}
val slaveBuffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
val slaveNode: TLInwardNode = DisableMonitors { implicit p => if (boundaryBuffers) {
rocket.slaveNode :*= slaveBuffer.node
slaveBuffer.node
} else { rocket.slaveNode } }
val slaveNode: TLInwardNode = crossing match {
case _: SynchronousCrossing => rocket.slaveNode // requirement already checked
case _: AsynchronousCrossing => rocket.slaveNode
case _: RationalCrossing =>
if (params.boundaryBuffers) {
DisableMonitors { implicit p => rocket.slaveNode :*= slaveBuffer.node }
} else {
rocket.slaveNode
}
}
val intXbar = LazyModule(new IntXbar)
rocket.intNode := intXbar.intnode