riscv/rocket-chip
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rocket: clarify intent of boundaryBuffers and move to RocketTile

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This commit is contained in:
Wesley W. Terpstra
2017-10-26 13:52:34 -07:00
parent e76e0f6dce
commit 9e33ccdb05
2 changed files with 30 additions and 15 deletions
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6
src/main/scala/coreplex/RocketCoreplex.scala
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@ -57,8 +57,7 @@ case class TileSlavePortParams(
case class RocketCrossingParams(
crossingType: CoreplexClockCrossing = SynchronousCrossing(),
master: TileMasterPortParams = TileMasterPortParams(),
slave: TileSlavePortParams = TileSlavePortParams(),
boundaryBuffers: Boolean = false) {
slave: TileSlavePortParams = TileSlavePortParams()) {
def knownRatio: Option[Int] = crossingType match {
case RationalCrossing(_) => Some(2)
case _ => None
@ -92,8 +91,7 @@ trait HasRocketTiles extends HasTiles
// in the global Parameters about the specific tile being built now
val wrapper = LazyModule(new RocketTileWrapper(
params = tp,
crossing = crossing.crossingType,
boundaryBuffers = crossing.boundaryBuffers
crossing = crossing.crossingType
)(p.alterPartial {
case TileKey => tp
case BuildRoCC => tp.rocc