riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into debug_v013_pr

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Megan Wachs committed 2017-03-30 08:01:11 -07:00
2 parents a14b7b5794 c61714a465
commit 9de06f8c83
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src/main/scala/rocketchip/BaseTop.scala
+1 -1
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@@ -35,7 +35,7 @@ trait HasTopLevelNetworks extends HasPeripheryParameters {
val socBus = LazyModule(new TLXbar) // Wide or unordered-access slave devices (TL-UH)
val peripheryBus = LazyModule(new TLXbar) // Narrow and ordered-access slave devices (TL-UL)
val intBus = LazyModule(new IntXbar) // Interrupts
val intBus = LazyModule(new IntXbar) // Device and global external interrupts
val fsb = LazyModule(new TLBuffer(BufferParams.none)) // Master devices talking to the frontside of the L2
val bsb = LazyModule(new TLBuffer(BufferParams.none)) // Slave devices talking to the backside of the L2
val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM