riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into debug_v013_pr

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This commit is contained in:
Megan Wachs
2017-03-30 08:01:11 -07:00
parent a14b7b5794 c61714a465
commit 9de06f8c83
16 changed files with 130 additions and 60 deletions
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2
src/main/scala/coreplex/CoreplexNetwork.scala
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@ -66,7 +66,7 @@ trait CoreplexNetwork extends HasCoreplexParameters {
Description("soc", Map(
"#address-cells" -> width,
"#size-cells" -> width,
"compatible" -> (p(DTSModel) +: p(DTSCompat)).map(s => ResourceString(s + "-soc")),
"compatible" -> ((p(DTSModel) +: p(DTSCompat)).map(s => ResourceString(s + "-soc")) :+ ResourceString("simple-bus")),
"ranges" -> Nil))
}
}

22
src/main/scala/coreplex/RocketTiles.scala
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@ -8,6 +8,7 @@ import diplomacy._
import rocket._
import tile._
import uncore.tilelink2._
import util._
sealed trait ClockCrossing
case object Synchronous extends ClockCrossing
@ -21,12 +22,17 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val module: HasRocketTilesModule
private val crossing = p(RocketCrossing)
private val configs = p(RocketTilesKey)
val tileParams = p(RocketTilesKey)
// TODO: hack to fix deduplication; see PR https://github.com/ucb-bar/berkeley-hardfloat/pull/14
hardfloat.consts
// Handle interrupts to be routed directly into each tile
val localIntNodes = tileParams map { t =>
(t.core.nLocalInterrupts > 0).option(IntInputNode())
}
val rocketWires: Seq[HasRocketTilesBundle => Unit] = configs.zipWithIndex.map { case (c, i) =>
// Make a function for each tile that will wire it to coreplex devices and crossbars,
// according to the specified type of clock crossing.
val wiringTuple = localIntNodes.zip(tileParams).zipWithIndex
val rocketWires: Seq[HasRocketTilesBundle => Unit] = wiringTuple.map { case ((lip, c), i) =>
val pWithExtra = p.alterPartial {
case TileKey => c
case BuildRoCC => c.rocc
@ -34,10 +40,11 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
}
val intBar = LazyModule(new IntXbar)
intBar.intnode := debug.intnode // Debug Interrupt
intBar.intnode := clint.intnode // msip+mtip
intBar.intnode := plic.intnode // meip
intBar.intnode := debug.intnode // debug
intBar.intnode := clint.intnode // msip+mtip
intBar.intnode := plic.intnode // meip
if (c.core.useVM) intBar.intnode := plic.intnode // seip
lip.foreach { intBar.intnode := _ } // lip
crossing match {
case Synchronous => {
@ -97,6 +104,7 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
trait HasRocketTilesBundle extends CoreplexRISCVPlatformBundle {
val outer: HasRocketTiles
val local_interrupts = HeterogeneousBag(outer.localIntNodes.flatten.map(_.bundleIn))
val tcrs = Vec(p(RocketTilesKey).size, new Bundle {
val clock = Clock(INPUT)
val reset = Bool(INPUT)