diff --git a/groundtest b/groundtest index 13a1b91e..82a6f060 160000 --- a/groundtest +++ b/groundtest @@ -1 +1 @@ -Subproject commit 13a1b91e9e729f6fcec7f7dc2458ec33e728e98f +Subproject commit 82a6f060db93d71ff6d2d44bde9ff8e4e1bf4bef diff --git a/hardfloat b/hardfloat index 0b811e0e..b7644fad 160000 --- a/hardfloat +++ b/hardfloat @@ -1 +1 @@ -Subproject commit 0b811e0edbc670e0154e6f93ea4aa73f867e1d8f +Subproject commit b7644fadecd6b11b8dc7b041662feb7bca0c656b diff --git a/riscv-tools b/riscv-tools index 7f9d6b85..34a245b9 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 7f9d6b85f0ad3cdd2eed160ae24326abbe6f4768 +Subproject commit 34a245b943bcae60b6ccece8aba86670cd0f2631 diff --git a/rocket b/rocket index c79f2454..7c3baa0f 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit c79f2454abff77a043cca3124151f31f0b76e57f +Subproject commit 7c3baa0ff68b4d8f5732c498da907e58e96bbcf2 diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index f25f113e..adcfc7e0 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -27,49 +27,33 @@ class DefaultConfig extends Config ( val scr = AddrMapEntry("scr", None, MemSize(scrSize, AddrMapConsts.RW)) new AddrMap(deviceTree +: csrs :+ scr) } - def makeDeviceTree() = { + def makeConfigString() = { val addrMap = new AddrHashMap(site(GlobalAddrMap), site(MMIOBase)) - val devices = site(GlobalDeviceSet) - val dt = new DeviceTreeGenerator - dt.beginNode("") - dt.addProp("#address-cells", 2) - dt.addProp("#size-cells", 2) - dt.addProp("model", "Rocket-Chip") - dt.beginNode("memory@0") - dt.addProp("device_type", "memory") - dt.addReg(0, site(MMIOBase).toLong) - dt.endNode() - dt.beginNode("cpus") - dt.addProp("#address-cells", 2) - dt.addProp("#size-cells", 2) - for (i <- 0 until site(NTiles)) { - val csrs = addrMap(s"conf:csr$i") - dt.beginNode(s"cpu@${csrs.start.toLong.toHexString}") - dt.addProp("device_type", "cpu") - dt.addProp("compatible", "riscv") - dt.addProp("isa", s"rv${site(XLen)}") - dt.addReg(csrs.start.toLong) - dt.endNode() - } - dt.endNode() - val scrs = addrMap("conf:scr") - dt.beginNode(s"scr@${scrs.start.toLong.toHexString}") - dt.addProp("device_type", "scr") - dt.addProp("compatible", "riscv") - dt.addProp("protection", scrs.prot) - dt.addReg(scrs.start.toLong, scrs.size.toLong) - dt.endNode() - for (dev <- devices.toSeq) { - val entry = addrMap(s"devices:${dev.name}") - dt.beginNode(s"${dev.name}@${entry.start}") - dt.addProp("device_type", s"${dev.dtype}") - dt.addProp("compatible", "riscv") - dt.addProp("protection", entry.prot) - dt.addReg(entry.start.toLong, entry.size.toLong) - dt.endNode() - } - dt.endNode() - dt.toArray() + val xLen = site(XLen) + val res = new StringBuilder + res append "platform {\n" + res append " vendor ucb;\n" + res append " arch rocket;\n" + res append "};\n" + res append "ram {\n" + res append " 0 {\n" + res append " addr 0;\n" + res append s" size 0x${site(MMIOBase).toString(16)};\n" + res append " };\n" + res append "};\n" + res append "core {\n" + for (i <- 0 until site(NTiles)) { + val csrAddr = addrMap(s"conf:csr$i").start + res append s" $i {\n" + res append " 0 {\n" + res append s" isa rv$xLen;\n" + res append s" addr 0x${csrAddr.toString(16)};\n" + res append " };\n" + res append " };\n" + } + res append "};\n" + res append '\u0000' + res.toString.getBytes } pname match { case HtifKey => HtifParameters( @@ -189,7 +173,9 @@ class DefaultConfig extends Config ( case CoreInstBits => 32 case CoreDataBits => site(XLen) case NCustomMRWCSRs => 0 - case MtvecInit => BigInt(0x100) + case ResetVector => BigInt(0x0) + case MtvecInit => BigInt(0x8) + case MtvecWritable => false //Uncore Paramters case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients @@ -234,7 +220,7 @@ class DefaultConfig extends Config ( case UseBackupMemoryPort => false case UseHtifClockDiv => true case MMIOBase => Dump("MEM_SIZE", BigInt(1L << 30)) // 1 GB - case DeviceTree => makeDeviceTree() + case ConfigString => makeConfigString() case GlobalAddrMap => { AddrMap( AddrMapEntry("conf", None, diff --git a/src/main/scala/DeviceTree.scala b/src/main/scala/DeviceTree.scala deleted file mode 100644 index 7d98a238..00000000 --- a/src/main/scala/DeviceTree.scala +++ /dev/null @@ -1,80 +0,0 @@ -package rocketchip - -case object DeviceTree extends cde.Field[Array[Byte]] - -private class StringTable { - private val strings = collection.mutable.HashMap[String, Int]() - private val data = collection.mutable.ArrayBuffer[Byte]() - - def add(x: String) = { - if (!strings.contains(x)) { - strings(x) = data.length - data ++= x.getBytes - data += 0 - } - strings(x) - } - - def toArray = data.toArray -} - -class DeviceTreeGenerator { - def beginNode(name: String): Unit = { - append(pack(1)) - append(pack(name)) - } - def endNode(): Unit = append(pack(2)) - def addProp(name: String, data: Int): Unit = addProp(name, pack(data), 4) - def addProp(name: String, data: String): Unit = - addProp(name, pack(data), data.getBytes.length+1) - def addReg(values: Long*): Unit = { - val seq = values.toSeq - val buf = java.nio.ByteBuffer.allocate(seq.length*8) - seq foreach buf.putLong - addProp("reg", buf.array, buf.array.length) - } - def toArray(): Array[Byte] = { - append(pack(9)) - val structArray = os.toByteArray - val stringArray = strings.toArray - - val headerSize = 40 - val rsvMap = Array.fill[Byte](16)(0) - val rsvMapOffset = headerSize - val structOffset = headerSize + rsvMap.length - val stringOffset = structOffset + structArray.length - val totalSize = stringOffset + stringArray.length - - os.reset() - append(pack(0xd00dfeed)) // magic - append(pack(totalSize)) - append(pack(structOffset)) - append(pack(stringOffset)) - append(pack(rsvMapOffset)) - append(pack(17)) // version - append(pack(16)) // compatible version - append(pack(0)) // boot cpuid - append(pack(stringArray.length)) - append(pack(structArray.length)) - append(rsvMap) - append(structArray) - append(stringArray) - - val res = os.toByteArray - os.reset - res - } - - private val os = new java.io.ByteArrayOutputStream - private val strings = new StringTable - private def pack(x: String) = x.getBytes.padTo((x.getBytes.length+4)/4*4, 0.toByte) - private def pack(x: Int) = java.nio.ByteBuffer.allocate(4).putInt(x).array - private def append(x: Array[Byte]) = os.write(x, 0, x.length) - private def addProp(name: String, data: Array[Byte], length: Int) = { - require(data.length % 4 == 0) - append(pack(3)) - append(pack(length)) - append(pack(strings.add(name))) - append(data) - } -} diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index e45189aa..fa943da6 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -35,6 +35,8 @@ case object BuildL2CoherenceManager extends Field[(Int, Parameters) => Coherence case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]] /** Enable DMA engine */ case object UseDma extends Field[Boolean] +/** A string describing on-chip devices, readable by target software */ +case object ConfigString extends cde.Field[Array[Byte]] case object UseStreamLoopback extends Field[Boolean] case object StreamLoopbackSize extends Field[Int] @@ -186,7 +188,7 @@ class Uncore(implicit val p: Parameters) extends Module "MEMORY_CHANNEL_MUX_SELECT") outmemsys.io.memory_channel_mux_select := memory_channel_mux_select - val deviceTree = Module(new NastiROM(p(DeviceTree).toSeq)) + val deviceTree = Module(new NastiROM(p(ConfigString).toSeq)) deviceTree.io <> outmemsys.io.deviceTree // Wire the htif to the memory port(s) and host interface @@ -267,10 +269,13 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe val nMasters = (if (dmaOpt.isEmpty) 2 else 3) val nSlaves = addrHashMap.nEntries + // TODO: the code to print this stuff should live somewhere else println("Generated Address Map") for ((name, base, size, _) <- addrHashMap.sortedEntries) { println(f"\t$name%s $base%x - ${base + size - 1}%x") } + println("Generated Configuration String") + println(new String(p(ConfigString))) val mmio_ic = Module(new NastiRecursiveInterconnect(nMasters, nSlaves, addrMap, mmioBase)) diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala index e3dd2491..7e157d34 100644 --- a/src/main/scala/Testing.scala +++ b/src/main/scala/Testing.scala @@ -220,8 +220,8 @@ object TestGenerator extends App with FileSystemUtilities { val v = createOutputFile(configClassName + ".knb") v.write(world.getKnobs) v.close - val d = new java.io.FileOutputStream(Driver.targetDir + "/" + configClassName + ".dtb") - d.write(paramsFromConfig(DeviceTree)) + val d = new java.io.FileOutputStream(Driver.targetDir + "/" + configClassName + ".cfg") + d.write(paramsFromConfig(ConfigString)) d.close val w = createOutputFile(configClassName + ".cst") w.write(world.getConstraints) diff --git a/uncore b/uncore index 97ec0771..2e2e297e 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit 97ec0771a582e83786881ac42ea67e5bf8267305 +Subproject commit 2e2e297ee739902b63b8e04e3a7ad5a3ef87c28b