From 9d89d2a5580f839c73e34c1a14e6e93689834644 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Thu, 10 Sep 2015 17:53:17 -0700 Subject: [PATCH] get rid of MemIO -> TileLink converters --- uncore/src/main/scala/tilelink.scala | 264 --------------------------- 1 file changed, 264 deletions(-) diff --git a/uncore/src/main/scala/tilelink.scala b/uncore/src/main/scala/tilelink.scala index 3228b9a3..ee176280 100644 --- a/uncore/src/main/scala/tilelink.scala +++ b/uncore/src/main/scala/tilelink.scala @@ -1513,267 +1513,3 @@ class NASTIMasterIOTileLinkIOConverter extends TLModule with NASTIParameters { addr_beat = UInt(0), data = Bits(0)) } - -class MemPipeIOTileLinkIOConverter(outstanding: Int) extends MIFModule { - val io = new Bundle { - val tl = new ManagerTileLinkIO - val mem = new MemPipeIO - } - - val a = Module(new MemIOTileLinkIOConverter(1)) - val b = Module(new MemPipeIOMemIOConverter(outstanding)) - io.tl <> a.io.tl - b.io.cpu.req_cmd <> Queue(a.io.mem.req_cmd, 2, pipe=true) - b.io.cpu.req_data <> Queue(a.io.mem.req_data, mifDataBeats, pipe=true) - a.io.mem.resp <> b.io.cpu.resp - io.mem <> b.io.mem -} - -//Adapter betweewn an UncachedTileLinkIO and a mem controller MemIO -class MemIOTileLinkIOConverter(qDepth: Int) extends TLModule with MIFParameters { - val io = new Bundle { - val tl = new ManagerTileLinkIO - val mem = new MemIO - } - val dataBits = tlDataBits*tlDataBeats - val dstIdBits = params(LNHeaderBits) - require(tlDataBits*tlDataBeats == mifDataBits*mifDataBeats, "Data sizes between LLC and MC don't agree") - require(dstIdBits + tlClientXactIdBits < mifTagBits, "MemIO converter is going truncate tags: " + dstIdBits + " + " + tlClientXactIdBits + " >= " + mifTagBits) - - io.tl.acquire.ready := Bool(false) - io.tl.probe.valid := Bool(false) - io.tl.release.ready := Bool(false) - io.tl.finish.ready := Bool(true) - io.mem.resp.ready := Bool(false) - - val gnt_arb = Module(new Arbiter(new GrantToDst, 2)) - io.tl.grant <> gnt_arb.io.out - - val dst_off = dstIdBits + tlClientXactIdBits - val acq_has_data = io.tl.acquire.bits.hasData() - val rel_has_data = io.tl.release.bits.hasData() - - // Decompose outgoing TL Acquires into MemIO cmd and data - val active_out = Reg(init=Bool(false)) - val cmd_sent_out = Reg(init=Bool(false)) - val tag_out = Reg(UInt(width = mifTagBits)) - val addr_out = Reg(UInt(width = mifAddrBits)) - val has_data = Reg(init=Bool(false)) - val data_from_rel = Reg(init=Bool(false)) - val (tl_cnt_out, tl_wrap_out) = - Counter((io.tl.acquire.fire() && acq_has_data) || - (io.tl.release.fire() && rel_has_data), tlDataBeats) - val tl_done_out = Reg(init=Bool(false)) - val make_grant_ack = Reg(init=Bool(false)) - - gnt_arb.io.in(1).valid := Bool(false) - gnt_arb.io.in(1).bits := Grant( - dst = (if(dstIdBits > 0) tag_out(dst_off, tlClientXactIdBits + 1) else UInt(0)), - is_builtin_type = Bool(true), - g_type = Mux(data_from_rel, Grant.voluntaryAckType, Grant.putAckType), - client_xact_id = tag_out >> 1, - manager_xact_id = UInt(0)) - - if(tlDataBits != mifDataBits || tlDataBeats != mifDataBeats) { - val mem_cmd_q = Module(new Queue(new MemReqCmd, qDepth)) - val mem_data_q = Module(new Queue(new MemData, qDepth)) - mem_cmd_q.io.enq.valid := Bool(false) - mem_data_q.io.enq.valid := Bool(false) - val (mif_cnt_out, mif_wrap_out) = Counter(mem_data_q.io.enq.fire(), mifDataBeats) - val mif_done_out = Reg(init=Bool(false)) - val tl_buf_out = Reg(Vec(io.tl.acquire.bits.data, tlDataBeats)) - val mif_buf_out = Vec(new MemData, mifDataBeats) - mif_buf_out := mif_buf_out.fromBits(tl_buf_out.toBits) - val mif_prog_out = (mif_cnt_out+UInt(1, width = log2Up(mifDataBeats+1)))*UInt(mifDataBits) - val tl_prog_out = tl_cnt_out*UInt(tlDataBits) - - when(!active_out){ - io.tl.release.ready := Bool(true) - io.tl.acquire.ready := !io.tl.release.valid - when(io.tl.release.valid) { - active_out := Bool(true) - cmd_sent_out := Bool(false) - tag_out := Cat(io.tl.release.bits.client_xact_id, - io.tl.release.bits.isVoluntary()) - addr_out := io.tl.release.bits.addr_block - has_data := rel_has_data - data_from_rel := Bool(true) - make_grant_ack := io.tl.release.bits.requiresAck() - tl_done_out := tl_wrap_out - tl_buf_out(tl_cnt_out) := io.tl.release.bits.data - } .elsewhen(io.tl.acquire.valid) { - active_out := Bool(true) - cmd_sent_out := Bool(false) - tag_out := Cat(io.tl.release.bits.client_id, - io.tl.acquire.bits.client_xact_id, - io.tl.acquire.bits.isBuiltInType()) - addr_out := io.tl.acquire.bits.addr_block - has_data := acq_has_data - data_from_rel := Bool(false) - make_grant_ack := acq_has_data - tl_done_out := tl_wrap_out - tl_buf_out(tl_cnt_out) := io.tl.acquire.bits.data - } - } - when(active_out) { - mem_cmd_q.io.enq.valid := !cmd_sent_out - cmd_sent_out := cmd_sent_out || mem_cmd_q.io.enq.fire() - when(has_data) { - when(!tl_done_out) { - io.tl.acquire.ready := Bool(true) - when(io.tl.acquire.valid) { - tl_buf_out(tl_cnt_out) := Mux(data_from_rel, - io.tl.release.bits.data, - io.tl.acquire.bits.data) - } - } - when(!mif_done_out) { - mem_data_q.io.enq.valid := tl_done_out || mif_prog_out <= tl_prog_out - } - } - when(tl_wrap_out) { tl_done_out := Bool(true) } - when(mif_wrap_out) { mif_done_out := Bool(true) } - when(tl_done_out && make_grant_ack) { - gnt_arb.io.in(1).valid := Bool(true) - when(gnt_arb.io.in(1).ready) { make_grant_ack := Bool(false) } - } - when(cmd_sent_out && (!has_data || mif_done_out) && !make_grant_ack) { - active_out := Bool(false) - } - } - - mem_cmd_q.io.enq.bits.rw := has_data - mem_cmd_q.io.enq.bits.tag := tag_out - mem_cmd_q.io.enq.bits.addr := addr_out - mem_data_q.io.enq.bits.data := mif_buf_out(mif_cnt_out).data - io.mem.req_cmd <> mem_cmd_q.io.deq - io.mem.req_data <> mem_data_q.io.deq - } else { // Don't make the data buffers and try to flow cmd and data - io.mem.req_cmd.valid := Bool(false) - io.mem.req_data.valid := Bool(false) - io.mem.req_cmd.bits.rw := has_data - io.mem.req_cmd.bits.tag := tag_out - io.mem.req_cmd.bits.addr := addr_out - io.mem.req_data.bits.data := Mux(data_from_rel, - io.tl.release.bits.data, - io.tl.acquire.bits.data) - when(!active_out){ - io.tl.release.ready := io.mem.req_data.ready - io.tl.acquire.ready := io.mem.req_data.ready && !io.tl.release.valid - io.mem.req_data.valid := (io.tl.release.valid && rel_has_data) || - (io.tl.acquire.valid && acq_has_data) - when(io.mem.req_data.ready && (io.tl.release.valid || io.tl.acquire.valid)) { - active_out := !io.mem.req_cmd.ready || io.mem.req_data.valid - io.mem.req_cmd.valid := Bool(true) - cmd_sent_out := io.mem.req_cmd.ready - tl_done_out := tl_wrap_out - when(io.tl.release.valid) { - data_from_rel := Bool(true) - make_grant_ack := io.tl.release.bits.requiresAck() - io.mem.req_data.bits.data := io.tl.release.bits.data - val tag = Cat(io.tl.release.bits.client_id, - io.tl.release.bits.client_xact_id, - io.tl.release.bits.isVoluntary()) - val addr = io.tl.release.bits.addr_block - io.mem.req_cmd.bits.tag := tag - io.mem.req_cmd.bits.addr := addr - io.mem.req_cmd.bits.rw := rel_has_data - tag_out := tag - addr_out := addr - has_data := rel_has_data - } .elsewhen(io.tl.acquire.valid) { - data_from_rel := Bool(false) - make_grant_ack := acq_has_data // i.e. is it a Put - io.mem.req_data.bits.data := io.tl.acquire.bits.data - io.mem.req_cmd.bits.rw := acq_has_data - val tag = Cat(io.tl.acquire.bits.client_id, - io.tl.acquire.bits.client_xact_id, - io.tl.acquire.bits.isBuiltInType()) - val addr = io.tl.acquire.bits.addr_block - io.mem.req_cmd.bits.tag := tag - io.mem.req_cmd.bits.addr := addr - io.mem.req_cmd.bits.rw := acq_has_data - tag_out := tag - addr_out := addr - has_data := acq_has_data - } - } - } - when(active_out) { - io.mem.req_cmd.valid := !cmd_sent_out - cmd_sent_out := cmd_sent_out || io.mem.req_cmd.fire() - when(has_data && !tl_done_out) { - when(data_from_rel) { - io.tl.release.ready := io.mem.req_data.ready - io.mem.req_data.valid := io.tl.release.valid - } .otherwise { - io.tl.acquire.ready := io.mem.req_data.ready - io.mem.req_data.valid := io.tl.acquire.valid - } - } - when(tl_wrap_out) { tl_done_out := Bool(true) } - when(tl_done_out && make_grant_ack) { - gnt_arb.io.in(1).valid := Bool(true) // TODO: grants for voluntary acks? - when(gnt_arb.io.in(1).ready) { make_grant_ack := Bool(false) } - } - when(cmd_sent_out && (!has_data || tl_done_out) && !make_grant_ack) { - active_out := Bool(false) - } - } - } - - // Aggregate incoming MemIO responses into TL Grants - val active_in = Reg(init=Bool(false)) - val (tl_cnt_in, tl_wrap_in) = Counter(io.tl.grant.fire() && io.tl.grant.bits.hasMultibeatData(), tlDataBeats) - val tag_in = Reg(UInt(width = mifTagBits)) - - if(tlDataBits != mifDataBits || tlDataBeats != mifDataBeats) { - val (mif_cnt_in, mif_wrap_in) = Counter(io.mem.resp.fire(), mifDataBeats) // TODO: Assumes all resps have data - val mif_done_in = Reg(init=Bool(false)) - val mif_buf_in = Reg(Vec(new MemData, mifDataBeats)) - val tl_buf_in = Vec(io.tl.acquire.bits.data, tlDataBeats) - tl_buf_in := tl_buf_in.fromBits(mif_buf_in.toBits) - val tl_prog_in = (tl_cnt_in+UInt(1, width = log2Up(tlDataBeats+1)))*UInt(tlDataBits) - val mif_prog_in = mif_cnt_in*UInt(mifDataBits) - gnt_arb.io.in(0).bits := Grant( - dst = (if(dstIdBits > 0) tag_in(dst_off, tlClientXactIdBits + 1) else UInt(0)), - is_builtin_type = tag_in(0), - g_type = Mux(tag_in(0), Grant.getDataBlockType, UInt(0)), // TODO: Assumes MI or MEI protocol - client_xact_id = tag_in >> 1, - manager_xact_id = UInt(0), - addr_beat = tl_cnt_in, - data = tl_buf_in(tl_cnt_in)) - - when(!active_in) { - io.mem.resp.ready := Bool(true) - when(io.mem.resp.valid) { - active_in := Bool(true) - mif_done_in := mif_wrap_in - tag_in := io.mem.resp.bits.tag - mif_buf_in(tl_cnt_in).data := io.mem.resp.bits.data - } - } - when(active_in) { - gnt_arb.io.in(0).valid := mif_done_in || tl_prog_in <= mif_prog_in - when(!mif_done_in) { - io.mem.resp.ready := Bool(true) - when(io.mem.resp.valid) { - mif_buf_in(mif_cnt_in).data := io.mem.resp.bits.data - } - } - when(mif_wrap_in) { mif_done_in := Bool(true) } - when(tl_wrap_in) { active_in := Bool(false) } - } - } else { // Don't generate all the uneeded data buffers and flow resp - gnt_arb.io.in(0).valid := io.mem.resp.valid - io.mem.resp.ready := gnt_arb.io.in(0).ready - gnt_arb.io.in(0).bits := Grant( - dst = (if(dstIdBits > 0) io.mem.resp.bits.tag(dst_off, tlClientXactIdBits + 1) else UInt(0)), - is_builtin_type = io.mem.resp.bits.tag(0), - g_type = Mux(io.mem.resp.bits.tag(0), Grant.getDataBlockType, UInt(0)), // TODO: Assumes MI or MEI protocol - client_xact_id = io.mem.resp.bits.tag >> 1, - manager_xact_id = UInt(0), - addr_beat = tl_cnt_in, - data = io.mem.resp.bits.data) - } -}