tilelink2: AddressSet always has an assigned base address

The consensus seems to be that TileLink should not be assigning
addresses dynamically. The reasons:

1. We can come up with another scheme for assigning addresses that is
   independent of TileLink.  This decoupling is good, because it would
   allow us to use the same mechanism for different buses in the SoC.

2. The informational flow of addresses is more likely to naturally follow
   the module hierarchy than the TileLike bus topology. Thus, it seems
   better to pass address parameterization using Module constructors.

3. Addresses are still checked by TileLink, so using a Module-centric
   flow for addresses will not pose a correctness concern.

4. An address need only be provided to a slave on its construction and
   TileLink parameterization spreads this globally. Thus, the burden to
   manually assign an address is low.

uncore/src/main/scala/tilelink2/RegisterRouter.scala

@@ -74,10 +74,10 @@ class TLRegModule[P, B <: Bundle](val params: P, bundleBuilder: => B, router: TL
 }
 
 class TLRegisterRouter[B <: Bundle, M <: LazyModuleImp]
-   (address: Option[BigInt] = None, size: BigInt = 4096, concurrency: Option[Int] = None, beatBytes: Int = 4)
+   (base: BigInt, size: BigInt = 4096, concurrency: Option[Int] = None, beatBytes: Int = 4)
    (bundleBuilder: Vec[TLBundle] => B)
    (moduleBuilder: (=> B, TLRegisterRouterBase) => M)
-  extends TLRegisterRouterBase(AddressSet(size-1, address), concurrency, beatBytes)
+  extends TLRegisterRouterBase(AddressSet(base, size-1), concurrency, beatBytes)
 {
   require (size % 4096 == 0) // devices should be 4K aligned
   require (isPow2(size))