tilelink2: shave off a few more firrtl monitor lines

2016-08-22 16:43:00 -07:00
parent af29595979
commit 9c62f5d9c1
1 changed files with 3 additions and 1 deletions
--- a/uncore/src/main/scala/tilelink2/Parameters.scala
+++ b/uncore/src/main/scala/tilelink2/Parameters.scala
@@ -315,9 +315,11 @@ case class TLEdgeParameters(
      } else {
        val sub = helper(i-1)
        val size = lgSize === UInt(lgBytes - i)
+        val bit = address(lgBytes - i)
+        val nbit = !bit
        Seq.tabulate (1 << i) { j =>
          val (sub_acc, sub_eq) = sub(j/2)
-          val eq = sub_eq && address(lgBytes - i) === Bool(j % 2 == 1)
+          val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
          val acc = sub_acc || (size && eq)
          (acc, eq)
        }