remove chip-specific uncore gunk
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a5bea4364f
commit
9c50621a19
@ -5,95 +5,14 @@ import Node._;
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import Constants._;
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import collection.mutable._
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class ioTop(htif_width: Int) extends Bundle {
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val debug = new ioDebug();
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val host = new ioHost(htif_width);
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val host_clk = Bool(OUTPUT)
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val mem_backup = new ioMemSerialized
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val mem_backup_en = Bool(INPUT)
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val mem_backup_clk = Bool(OUTPUT)
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val mem = new ioMemPipe
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}
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class ioUncore(htif_width: Int, ntiles: Int) extends Bundle {
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val debug = new ioDebug()
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val host = new ioHost(htif_width)
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val host_clk = Bool(OUTPUT)
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val mem_backup = new ioMemSerialized
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val mem_backup_en = Bool(INPUT)
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val mem_backup_clk = Bool(OUTPUT)
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val mem = new ioMemPipe
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val tiles = Vec(ntiles) { new ioTileLink() }.flip
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val htif = Vec(ntiles) { new ioHTIF() }.flip
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}
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class Uncore(htif_width: Int, ntiles: Int, co: CoherencePolicyWithUncached) extends Component
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{
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val clkdiv = 8
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val io = new ioUncore(htif_width, ntiles)
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val htif = new rocketHTIF(htif_width, NTILES, co)
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val hub = new CoherenceHubBroadcast(NTILES+1, co)
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val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) }
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val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
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val llc = new DRAMSideLLC(1024, 8, 4, llc_tag_leaf, llc_data_leaf)
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for (i <- 0 until NTILES) {
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hub.io.tiles(i) <> io.tiles(i)
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htif.io.cpu(i) <> io.htif(i)
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}
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hub.io.tiles(NTILES) <> htif.io.mem
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llc.io.cpu.req_cmd <> Queue(hub.io.mem.req_cmd)
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llc.io.cpu.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES)
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hub.io.mem.resp <> llc.io.cpu.resp
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// mux between main and backup memory ports
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val mem_serdes = new MemSerdes
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val mem_cmdq = (new queue(2)) { new MemReqCmd }
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mem_cmdq.io.enq <> llc.io.mem.req_cmd
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mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
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io.mem.req_cmd.valid := mem_cmdq.io.deq.valid && !io.mem_backup_en
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io.mem.req_cmd.bits := mem_cmdq.io.deq.bits
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mem_serdes.io.wide.req_cmd.valid := mem_cmdq.io.deq.valid && io.mem_backup_en
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mem_serdes.io.wide.req_cmd.bits := mem_cmdq.io.deq.bits
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val mem_dataq = (new queue(REFILL_CYCLES)) { new MemData }
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mem_dataq.io.enq <> llc.io.mem.req_data
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mem_dataq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_data.ready, io.mem.req_data.ready)
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io.mem.req_data.valid := mem_dataq.io.deq.valid && !io.mem_backup_en
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io.mem.req_data.bits := mem_dataq.io.deq.bits
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mem_serdes.io.wide.req_data.valid := mem_dataq.io.deq.valid && io.mem_backup_en
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mem_serdes.io.wide.req_data.bits := mem_dataq.io.deq.bits
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llc.io.mem.resp.valid := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.valid, io.mem.resp.valid)
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llc.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits)
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// pad out the HTIF using a divided clock
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val hio = (new slowIO(clkdiv)) { Bits(width = htif_width+1) }
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hio.io.out_fast.valid := htif.io.host.out.valid || mem_serdes.io.narrow.req.valid
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hio.io.out_fast.bits := Cat(htif.io.host.out.valid, Mux(htif.io.host.out.valid, htif.io.host.out.bits, mem_serdes.io.narrow.req.bits))
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htif.io.host.out.ready := hio.io.out_fast.ready
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mem_serdes.io.narrow.req.ready := hio.io.out_fast.ready && !htif.io.host.out.valid
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io.host.out.valid := hio.io.out_slow.valid && hio.io.out_slow.bits(htif_width)
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io.host.out.bits := hio.io.out_slow.bits
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io.mem_backup.req.valid := hio.io.out_slow.valid && !hio.io.out_slow.bits(htif_width)
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hio.io.out_slow.ready := Mux(hio.io.out_slow.bits(htif_width), io.host.out.ready, io.mem_backup.req.ready)
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val mem_backup_resp_valid = io.mem_backup_en && io.mem_backup.resp.valid
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hio.io.in_slow.valid := mem_backup_resp_valid || io.host.in.valid
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hio.io.in_slow.bits := Cat(mem_backup_resp_valid, io.host.in.bits)
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io.host.in.ready := hio.io.in_slow.ready
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mem_serdes.io.narrow.resp.valid := hio.io.in_fast.valid && hio.io.in_fast.bits(htif_width)
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mem_serdes.io.narrow.resp.bits := hio.io.in_fast.bits
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htif.io.host.in.valid := hio.io.in_fast.valid && !hio.io.in_fast.bits(htif_width)
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htif.io.host.in.bits := hio.io.in_fast.bits
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hio.io.in_fast.ready := Mux(hio.io.in_fast.bits(htif_width), Bool(true), htif.io.host.in.ready)
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io.host_clk := hio.io.clk_slow
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}
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class Top extends Component
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{
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val io = new Bundle {
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val debug = new ioDebug
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val host = new ioHost(HTIF_WIDTH)
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val mem = new ioMemPipe
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}
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val co = if(ENABLE_SHARING) {
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if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence
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else new MSICoherence
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@ -101,15 +20,21 @@ class Top extends Component
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if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
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else new MICoherence
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}
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val io = new ioTop(HTIF_WIDTH)
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val uncore = new Uncore(HTIF_WIDTH, NTILES, co)
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uncore.io <> io
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val htif = new rocketHTIF(HTIF_WIDTH, NTILES, co)
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val hub = new CoherenceHubBroadcast(NTILES+1, co)
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hub.io.tiles(NTILES) <> htif.io.mem
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io.host <> htif.io.host
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io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
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io.mem.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES)
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hub.io.mem.resp <> Pipe(io.mem.resp)
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Assert(hub.io.mem.resp.ready, "hub.io.mem.resp.ready")
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var error_mode = Bool(false)
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for (i <- 0 until NTILES) {
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val hl = uncore.io.htif(i)
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val tl = uncore.io.tiles(i)
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val hl = htif.io.cpu(i)
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val tl = hub.io.tiles(i)
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val tile = new Tile(co, resetSignal = hl.reset)
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tile.io.host.reset := Reg(Reg(hl.reset))
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