riscv/rocket-chip
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tile: remove global Field ResetVectorBits

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Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.
This commit is contained in:
Henry Cook
2017-09-01 17:50:54 -07:00
parent 3133c321b7
commit 9c0bfbd500
11 changed files with 58 additions and 53 deletions
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src/main/scala/coreplex/Configs.scala
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@ -18,7 +18,6 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
case ASIdBits => 0
case XLen => 64 // Applies to all cores
case ResetVectorBits => 32 // TODO: site(SharedMemoryTLEdge).bundle.addressBits
case MaxHartIdBits => log2Up(site(RocketTilesKey).size)
case BuildCore => (p: Parameters) => new Rocket()(p)
case RocketTilesKey => Nil // Will be added by partial configs found below