tile: remove global Field ResetVectorBits

Reset vector width is determined by systemBus.busView.
Also move some defs from HasCoreParameters to HasTileParameters.

src/main/scala/coreplex/Configs.scala

@@ -18,7 +18,6 @@ class BaseCoreplexConfig extends Config ((site, here, up) => {
   case PgLevels => if (site(XLen) == 64) 3 /* Sv39 */ else 2 /* Sv32 */
   case ASIdBits => 0
   case XLen => 64 // Applies to all cores
-  case ResetVectorBits => 32 // TODO: site(SharedMemoryTLEdge).bundle.addressBits
   case MaxHartIdBits => log2Up(site(RocketTilesKey).size)
   case BuildCore => (p: Parameters) => new Rocket()(p)
   case RocketTilesKey =>  Nil // Will be added by partial configs found below

src/main/scala/coreplex/ResetVector.scala

@@ -3,12 +3,9 @@
 package freechips.rocketchip.coreplex
 
 import Chisel._
-import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.tile.ResetVectorBits
 
 /** A single place for all tiles to find out the reset vector */
 trait HasResetVectorWire {
-  implicit val p: Parameters
-  val resetVectorBits = p(ResetVectorBits)
+  def resetVectorBits: Int
   val global_reset_vector = Wire(UInt(width = resetVectorBits))
 }

src/main/scala/coreplex/RocketCoreplex.scala

@@ -101,14 +101,19 @@ trait HasRocketTilesModuleImp extends LazyMultiIOModuleImp
     with HasResetVectorWire
     with HasPeripheryDebugModuleImp {
   val outer: HasRocketTiles
-  val rocket_tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs))
+
+  // TODO make this less gross and/or support tiles with differently sized reset vectors
+  def resetVectorBits: Int = outer.paddrBits
+  val rocket_tile_inputs = Wire(Vec(outer.nRocketTiles, new ClockedRocketTileInputs()(p.alterPartial {
+    case SharedMemoryTLEdge => outer.sharedMemoryTLEdge
+  })))
 
   // Unconditionally wire up the non-diplomatic tile inputs
   outer.rocket_tiles.map(_.module).zip(rocket_tile_inputs).foreach { case(tile, wire) =>
     tile.clock := wire.clock
     tile.reset := wire.reset
     tile.io.hartid := wire.hartid
-    tile.io.resetVector := wire.resetVector
+    tile.io.reset_vector := wire.reset_vector
   }
 
   // Default values for tile inputs; may be overriden in other traits
@@ -116,7 +121,7 @@ trait HasRocketTilesModuleImp extends LazyMultiIOModuleImp
     wire.clock := clock
     wire.reset := reset
     wire.hartid := UInt(i)
-    wire.resetVector := global_reset_vector
+    wire.reset_vector := global_reset_vector
   }
 }
 

src/main/scala/coreplex/SystemBus.scala

@@ -125,4 +125,5 @@ trait HasSystemBus extends HasInterruptBus {
   val sbus = new SystemBus(sbusParams)
 
   def sharedMemoryTLEdge: TLEdge = sbus.busView
+  def paddrBits: Int = sbus.busView.bundle.addressBits
 }