rocketchip: top-level systems are now multi-IO modules
Cake pattern only 2 layers instead of 3. Standardized naming convention. Comments for periphery mix-ins. Testharnesses use new periphery helper methods.
This commit is contained in:
Henry Cook
@@ -9,13 +9,8 @@ import rocketchip._
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import util._
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class TestHarness(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val success = Bool(OUTPUT)
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}
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val io = new Bundle { val success = Bool(OUTPUT) }
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val dut = Module(LazyModule(new GroundTestTop).module)
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io.success := dut.io.success
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val channels = p(coreplex.BankedL2Config).nMemoryChannels
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if (channels > 0) Module(LazyModule(new SimAXIMem(channels)).module).io.axi4 <> dut.io.mem_axi4
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io.success := dut.io_success
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dut.connectSimAXIMem()
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}
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@@ -3,15 +3,14 @@
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package groundtest
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import Chisel._
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import config._
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import diplomacy._
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import coreplex._
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import config.Parameters
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import diplomacy.LazyModule
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import rocketchip._
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class GroundTestTop(implicit p: Parameters) extends BaseTop
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with PeripheryMasterAXI4Mem
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with PeripheryTestRAM {
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override lazy val module = new GroundTestTopModule(this, () => new GroundTestTopBundle(this))
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class GroundTestTop(implicit p: Parameters) extends BaseSystem
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with HasPeripheryMasterAXI4MemPort
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with HasPeripheryTestRAMSlave {
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override lazy val module = new GroundTestTopModule(this)
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val coreplex = LazyModule(new GroundTestCoreplex)
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@@ -20,14 +19,8 @@ class GroundTestTop(implicit p: Parameters) extends BaseTop
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(mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel }
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}
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class GroundTestTopBundle[+L <: GroundTestTop](_outer: L) extends BaseTopBundle(_outer)
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with PeripheryMasterAXI4MemBundle
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with PeripheryTestRAMBundle {
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val success = Bool(OUTPUT)
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}
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class GroundTestTopModule[+L <: GroundTestTop, +B <: GroundTestTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
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with PeripheryMasterAXI4MemModule
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with PeripheryTestRAMModule {
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io.success := outer.coreplex.module.io.success
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class GroundTestTopModule[+L <: GroundTestTop](_outer: L) extends BaseSystemModule(_outer)
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with HasPeripheryMasterAXI4MemPortModuleImp {
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val io_success = IO(Bool(OUTPUT))
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io_success := outer.coreplex.module.io.success
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}
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@@ -1,71 +0,0 @@
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// See LICENSE.SiFive for license details.
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package rocketchip
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import Chisel._
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import config._
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import junctions._
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import diplomacy._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.devices._
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import util._
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import rocket._
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/** BareTop is the root class for creating a top-level RTL module */
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abstract class BareTop(implicit p: Parameters) extends LazyModule {
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ElaborationArtefacts.add("graphml", graphML)
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}
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abstract class BareTopBundle[+L <: BareTop](_outer: L) extends GenericParameterizedBundle(_outer) {
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val outer = _outer
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implicit val p = outer.p
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}
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abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyMultiIOModuleImp(_outer) {
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val outer = _outer
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val io = IO(_io())
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}
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/** HasTopLevelNetworks provides buses that will serve as attachment points,
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* for use in sub-traits that connect individual agents or external ports.
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*/
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trait HasTopLevelNetworks extends HasPeripheryParameters {
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val module: HasTopLevelNetworksModule
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val socBus = LazyModule(new TLXbar) // Wide or unordered-access slave devices (TL-UH)
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val peripheryBus = LazyModule(new TLXbar) // Narrow and ordered-access slave devices (TL-UL)
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val intBus = LazyModule(new IntXbar) // Device and global external interrupts
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val fsb = LazyModule(new TLBuffer(BufferParams.none)) // Master devices talking to the frontside of the L2
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val bsb = LazyModule(new TLBuffer(BufferParams.none)) // Slave devices talking to the backside of the L2
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val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM
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// The peripheryBus hangs off of socBus;
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// here we convert TL-UH -> TL-UL
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peripheryBus.node :=
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TLBuffer()(
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TLWidthWidget(socBusConfig.beatBytes)(
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TLAtomicAutomata(arithmetic = peripheryBusArithmetic)(
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socBus.node)))
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}
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trait HasTopLevelNetworksBundle extends HasPeripheryParameters {
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val outer: HasTopLevelNetworks
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}
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trait HasTopLevelNetworksModule extends HasPeripheryParameters {
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val outer: HasTopLevelNetworks
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val io: HasTopLevelNetworksBundle
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}
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/** Base Top class with no peripheral devices or ports added */
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abstract class BaseTop(implicit p: Parameters) extends BareTop
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with HasTopLevelNetworks {
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override val module: BaseTopModule[BaseTop, BaseTopBundle[BaseTop]]
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}
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abstract class BaseTopBundle[+L <: BaseTop](_outer: L) extends BareTopBundle(_outer)
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with HasTopLevelNetworksBundle
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abstract class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle[L]](_outer: L, _io: () => B) extends BareTopModule(_outer, _io)
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with HasTopLevelNetworksModule
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@@ -7,52 +7,34 @@ import config._
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import junctions._
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import rocketchip._
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/** Example Top with Periphery (w/o coreplex) */
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abstract class ExampleTop(implicit p: Parameters) extends BaseTop
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with PeripheryAsyncExtInterrupts
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with PeripheryErrorSlave
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with PeripheryMasterAXI4Mem
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with PeripheryMasterAXI4MMIO
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with PeripherySlaveAXI4 {
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override lazy val module = new ExampleTopModule(this, () => new ExampleTopBundle(this))
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/** Example system with periphery devices (w/o coreplex) */
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abstract class ExampleSystem(implicit p: Parameters) extends BaseSystem
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with HasPeripheryAsyncExtInterrupts
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with HasPeripheryMasterAXI4MemPort
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with HasPeripheryMasterAXI4MMIOPort
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with HasPeripherySlaveAXI4Port
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with HasPeripheryErrorSlave
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with HasPeripheryZeroSlave {
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override lazy val module = new ExampleSystemModule(this)
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}
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class ExampleTopBundle[+L <: ExampleTop](_outer: L) extends BaseTopBundle(_outer)
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with PeripheryExtInterruptsBundle
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with PeripheryErrorSlaveBundle
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with PeripheryMasterAXI4MemBundle
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with PeripheryMasterAXI4MMIOBundle
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with PeripherySlaveAXI4Bundle
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class ExampleSystemModule[+L <: ExampleSystem](_outer: L) extends BaseSystemModule(_outer)
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with HasPeripheryExtInterruptsModuleImp
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with HasPeripheryMasterAXI4MemPortModuleImp
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with HasPeripheryMasterAXI4MMIOPortModuleImp
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with HasPeripherySlaveAXI4PortModuleImp
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class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
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with PeripheryExtInterruptsModule
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with PeripheryErrorSlaveModule
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with PeripheryMasterAXI4MemModule
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with PeripheryMasterAXI4MMIOModule
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with PeripherySlaveAXI4Module
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class ExampleRocketTop(implicit p: Parameters) extends ExampleTop
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with PeripheryBootROM
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with PeripheryZero
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with PeripheryDebug
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with PeripheryCounter
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with HardwiredResetVector
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with RocketPlexMaster {
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override lazy val module = new ExampleRocketTopModule(this, () => new ExampleRocketTopBundle(this))
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/** Example Top with periphery and a Rocket coreplex */
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class ExampleRocketTop(implicit p: Parameters) extends ExampleSystem
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with HasPeripheryBootROM
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with HasPeripheryDebug
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with HasPeripheryRTCCounter
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with HasRocketPlexMaster {
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override lazy val module = new ExampleRocketTopModule(this)
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}
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class ExampleRocketTopBundle[+L <: ExampleRocketTop](_outer: L) extends ExampleTopBundle(_outer)
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with PeripheryBootROMBundle
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with PeripheryZeroBundle
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with PeripheryDebugBundle
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with PeripheryCounterBundle
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with HardwiredResetVectorBundle
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with RocketPlexMasterBundle
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class ExampleRocketTopModule[+L <: ExampleRocketTop, +B <: ExampleRocketTopBundle[L]](_outer: L, _io: () => B) extends ExampleTopModule(_outer, _io)
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with PeripheryBootROMModule
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with PeripheryZeroModule
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with PeripheryDebugModule
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with PeripheryCounterModule
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with HardwiredResetVectorModule
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with RocketPlexMasterModule
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class ExampleRocketTopModule[+L <: ExampleRocketTop](_outer: L) extends ExampleSystemModule(_outer)
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with HasPeripheryBootROMModuleImp
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with HasPeripheryDebugModuleImp
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with HasPeripheryRTCCounterModuleImp
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with HasRocketPlexMasterModuleImp
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@@ -6,12 +6,8 @@ import Chisel._
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import config._
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import coreplex._
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import diplomacy._
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import tile.XLen
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import uncore.tilelink2._
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import uncore.axi4._
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import uncore.converters._
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import uncore.devices._
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import uncore.util._
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import util._
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import scala.math.{min,max}
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@@ -47,80 +43,96 @@ trait HasPeripheryParameters {
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def cacheBlockBytes = p(CacheBlockBytes)
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def peripheryBusArithmetic = p(PeripheryBusArithmetic)
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def nMemoryChannels = p(coreplex.BankedL2Config).nMemoryChannels
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def nExtInterrupts = p(NExtTopInterrupts)
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}
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/////
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abstract trait PeripheryExtInterrupts {
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this: HasTopLevelNetworks =>
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/** HasSystemNetworks provides buses that will serve as attachment points,
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* for use in the following child traits that connect individual agents or external ports.
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*/
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trait HasSystemNetworks extends HasPeripheryParameters {
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val socBus = LazyModule(new TLXbar) // Wide or unordered-access slave devices (TL-UH)
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val peripheryBus = LazyModule(new TLXbar) // Narrow and ordered-access slave devices (TL-UL)
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val intBus = LazyModule(new IntXbar) // Device and global external interrupts
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val fsb = LazyModule(new TLBuffer(BufferParams.none)) // Master devices talking to the frontside of the L2
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val bsb = LazyModule(new TLBuffer(BufferParams.none)) // Slave devices talking to the backside of the L2
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val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM
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// The peripheryBus hangs off of socBus;
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// here we convert TL-UH -> TL-UL
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peripheryBus.node :=
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TLBuffer()(
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TLWidthWidget(socBusConfig.beatBytes)(
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TLAtomicAutomata(arithmetic = peripheryBusArithmetic)(
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socBus.node)))
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}
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/** This trait adds externally driven interrupts to the system.
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* However, it should not be used directly; instead one of the below
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* synchronization wiring child traits should be used.
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*/
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abstract trait HasPeripheryExtInterrupts extends HasSystemNetworks {
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private val device = new Device with DeviceInterrupts {
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def describe(resources: ResourceBindings): Description = {
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Description("soc/offchip-interrupts", describeInterrupts(resources))
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}
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}
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val nExtInterrupts = p(NExtTopInterrupts)
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val extInterrupts = IntInternalInputNode(IntSourcePortSimple(num = nExtInterrupts, resources = device.int))
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}
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trait PeripheryExtInterruptsBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryExtInterrupts
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} =>
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val interrupts = UInt(INPUT, width = outer.nExtInterrupts)
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}
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trait PeripheryExtInterruptsModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryExtInterrupts
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val io: PeripheryExtInterruptsBundle
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} =>
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outer.extInterrupts.bundleIn.flatten.zipWithIndex.foreach { case(o, i) => o := io.interrupts(i) }
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}
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// This trait should be used if the External Interrupts have NOT
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// already been synchronized
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// to the Periphery (PLIC) Clock.
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trait PeripheryAsyncExtInterrupts extends PeripheryExtInterrupts {
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this: HasTopLevelNetworks =>
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/** This trait should be used if the External Interrupts have NOT
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* already been synchronized to the Periphery (PLIC) Clock.
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*/
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trait HasPeripheryAsyncExtInterrupts extends HasPeripheryExtInterrupts {
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if (nExtInterrupts > 0) {
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val extInterruptXing = LazyModule(new IntXing)
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intBus.intnode := extInterruptXing.intnode
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extInterruptXing.intnode := extInterrupts
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}
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}
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// This trait can be used if the External Interrupts have already been synchronized
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// to the Periphery (PLIC) Clock.
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trait PeripherySyncExtInterrupts extends PeripheryExtInterrupts {
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this: HasTopLevelNetworks =>
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/** This trait can be used if the External Interrupts have already been synchronized
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* to the Periphery (PLIC) Clock.
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*/
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trait HasPeripherySyncExtInterrupts extends HasPeripheryExtInterrupts {
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if (nExtInterrupts > 0) {
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intBus.intnode := extInterrupts
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}
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}
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/////
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/** Common io name and methods for propagating or tying off the port bundle */
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trait HasPeripheryExtInterruptsBundle extends HasPeripheryParameters {
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val interrupts: UInt
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def tieOffInterrupts(dummy: Int = 1) {
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interrupts := UInt(0)
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}
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}
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/** This trait performs the translation from a UInt IO into Diplomatic Interrupts.
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* The wiring must be done in the concrete LazyModuleImp.
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*/
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trait HasPeripheryExtInterruptsModuleImp extends LazyMultiIOModuleImp with HasPeripheryExtInterruptsBundle {
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val outer: HasPeripheryExtInterrupts
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val interrupts = IO(UInt(INPUT, width = outer.nExtInterrupts))
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trait PeripheryMasterAXI4Mem {
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this: HasTopLevelNetworks =>
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val module: PeripheryMasterAXI4MemModule
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outer.extInterrupts.bundleIn.flatten.zipWithIndex.foreach { case(o, i) => o := interrupts(i) }
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}
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///// The following traits add ports to the sytem, in some cases converting to different interconnect standards
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/** Adds a port to the system intended to master an AXI4 DRAM controller. */
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trait HasPeripheryMasterAXI4MemPort extends HasSystemNetworks {
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val module: HasPeripheryMasterAXI4MemPortModuleImp
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private val config = p(ExtMem)
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private val channels = p(BankedL2Config).nMemoryChannels
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private val lineBytes = p(CacheBlockBytes)
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private val blockBytes = p(CacheBlockBytes)
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private val device = new MemoryDevice
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val mem_axi4 = AXI4BlindOutputNode(Seq.tabulate(channels) { channel =>
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val base = AddressSet(config.base, config.size-1)
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val filter = AddressSet(channel * lineBytes, ~((channels-1) * lineBytes))
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val filter = AddressSet(channel * blockBytes, ~((channels-1) * blockBytes))
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AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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@@ -148,56 +160,22 @@ trait PeripheryMasterAXI4Mem {
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}
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}
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trait PeripheryMasterAXI4MemBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryMasterAXI4Mem
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} =>
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val mem_axi4 = outer.mem_axi4.bundleOut
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}
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trait PeripheryMasterAXI4MemModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryMasterAXI4Mem
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val io: PeripheryMasterAXI4MemBundle
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} =>
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}
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/////
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trait PeripheryZero {
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this: HasTopLevelNetworks =>
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val module: PeripheryZeroModule
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private val config = p(ZeroConfig)
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private val address = AddressSet(config.base, config.size-1)
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private val lineBytes = p(CacheBlockBytes)
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val zeros = mem map { case xbar =>
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val zero = LazyModule(new TLZero(address, beatBytes = config.beatBytes))
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zero.node := TLFragmenter(config.beatBytes, lineBytes)(xbar.node)
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zero
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/** Common io name and methods for propagating or tying off the port bundle */
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trait HasPeripheryMasterAXI4MemPortBundle extends HasPeripheryParameters {
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val mem_axi4: HeterogeneousBag[AXI4Bundle]
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def connectSimAXIMem(dummy: Int = 1) = {
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if (nMemoryChannels > 0) Module(LazyModule(new SimAXIMem(nMemoryChannels)).module).io.axi4 <> mem_axi4
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}
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}
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trait PeripheryZeroBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryZero
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} =>
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/** Actually generates the corresponding IO in the concrete Module */
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trait HasPeripheryMasterAXI4MemPortModuleImp extends LazyMultiIOModuleImp with HasPeripheryMasterAXI4MemPortBundle {
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val outer: HasPeripheryMasterAXI4MemPort
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val mem_axi4 = IO(outer.mem_axi4.bundleOut)
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}
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trait PeripheryZeroModule {
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this: HasTopLevelNetworksModule {
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val outer: PeripheryZero
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val io: PeripheryZeroBundle
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} =>
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}
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/////
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// PeripheryMasterAXI4MMIO is an example, make your own cake pattern like this one.
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trait PeripheryMasterAXI4MMIO {
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this: HasTopLevelNetworks =>
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/** Adds a AXI4 port to the system intended to master an MMIO device bus */
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trait HasPeripheryMasterAXI4MMIOPort extends HasSystemNetworks {
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private val config = p(ExtBus)
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private val device = new SimpleDevice("mmio", Nil)
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val mmio_axi4 = AXI4BlindOutputNode(Seq(AXI4SlavePortParameters(
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@@ -219,25 +197,22 @@ trait PeripheryMasterAXI4MMIO {
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socBus.node))))))
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}
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trait PeripheryMasterAXI4MMIOBundle {
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this: HasTopLevelNetworksBundle {
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val outer: PeripheryMasterAXI4MMIO
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} =>
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val mmio_axi4 = outer.mmio_axi4.bundleOut
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/** Common io name and methods for propagating or tying off the port bundle */
|
||||
trait HasPeripheryMasterAXI4MMIOPortBundle extends HasPeripheryParameters {
|
||||
val mmio_axi4: HeterogeneousBag[AXI4Bundle]
|
||||
def connectSimAXIMMIO(dummy: Int = 1) {
|
||||
Module(LazyModule(new SimAXIMem(1, 4096)).module).io.axi4 <> mmio_axi4
|
||||
}
|
||||
}
|
||||
|
||||
trait PeripheryMasterAXI4MMIOModule {
|
||||
this: HasTopLevelNetworksModule {
|
||||
val outer: PeripheryMasterAXI4MMIO
|
||||
val io: PeripheryMasterAXI4MMIOBundle
|
||||
} =>
|
||||
// nothing to do
|
||||
/** Actually generates the corresponding IO in the concrete Module */
|
||||
trait HasPeripheryMasterAXI4MMIOPortModuleImp extends LazyMultiIOModuleImp with HasPeripheryMasterAXI4MMIOPortBundle {
|
||||
val outer: HasPeripheryMasterAXI4MMIOPort
|
||||
val mmio_axi4 = IO(outer.mmio_axi4.bundleOut)
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
// PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
|
||||
trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
|
||||
/** Adds an AXI4 port to the system intended to be a slave on an MMIO device bus */
|
||||
trait HasPeripherySlaveAXI4Port extends HasSystemNetworks {
|
||||
private val config = p(ExtIn)
|
||||
val l2FrontendAXI4Node = AXI4BlindInputNode(Seq(AXI4MasterPortParameters(
|
||||
masters = Seq(AXI4MasterParameters(
|
||||
@@ -254,23 +229,28 @@ trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
|
||||
l2FrontendAXI4Node)))))
|
||||
}
|
||||
|
||||
trait PeripherySlaveAXI4Bundle extends HasTopLevelNetworksBundle {
|
||||
val outer: PeripherySlaveAXI4
|
||||
val l2_frontend_bus_axi4 = outer.l2FrontendAXI4Node.bundleIn
|
||||
/** Common io name and methods for propagating or tying off the port bundle */
|
||||
trait HasPeripherySlaveAXI4PortBundle extends HasPeripheryParameters {
|
||||
val l2_frontend_bus_axi4: HeterogeneousBag[AXI4Bundle]
|
||||
def tieOffAXI4SlavePort(dummy: Int = 1) {
|
||||
l2_frontend_bus_axi4.foreach { l2_axi4 =>
|
||||
l2_axi4.ar.valid := Bool(false)
|
||||
l2_axi4.aw.valid := Bool(false)
|
||||
l2_axi4.w .valid := Bool(false)
|
||||
l2_axi4.r .ready := Bool(true)
|
||||
l2_axi4.b .ready := Bool(true)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
trait PeripherySlaveAXI4Module extends HasTopLevelNetworksModule {
|
||||
val outer: PeripherySlaveAXI4
|
||||
val io: PeripherySlaveAXI4Bundle
|
||||
// nothing to do
|
||||
/** Actually generates the corresponding IO in the concrete Module */
|
||||
trait HasPeripherySlaveAXI4PortModuleImp extends LazyMultiIOModuleImp with HasPeripherySlaveAXI4PortBundle {
|
||||
val outer: HasPeripherySlaveAXI4Port
|
||||
val l2_frontend_bus_axi4 = IO(outer.l2FrontendAXI4Node.bundleIn)
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
// Add an external TL-UL slave
|
||||
trait PeripheryMasterTLMMIO {
|
||||
this: HasTopLevelNetworks =>
|
||||
|
||||
/** Adds a TileLink port to the system intended to master an MMIO device bus */
|
||||
trait HasPeripheryMasterTLMMIOPort extends HasSystemNetworks {
|
||||
private val config = p(ExtBus)
|
||||
private val device = new SimpleDevice("mmio", Nil)
|
||||
val mmio_tl = TLBlindOutputNode(Seq(TLManagerPortParameters(
|
||||
@@ -290,25 +270,30 @@ trait PeripheryMasterTLMMIO {
|
||||
socBus.node)))
|
||||
}
|
||||
|
||||
trait PeripheryMasterTLMMIOBundle {
|
||||
this: HasTopLevelNetworksBundle {
|
||||
val outer: PeripheryMasterTLMMIO
|
||||
} =>
|
||||
val mmio_tl = outer.mmio_tl.bundleOut
|
||||
/** Common io name and methods for propagating or tying off the port bundle */
|
||||
trait HasPeripheryMasterTLMMIOPortBundle extends HasPeripheryParameters {
|
||||
val mmio_tl: HeterogeneousBag[TLBundle]
|
||||
def tieOffTLMMIO(dummy: Int = 1) {
|
||||
mmio_tl.foreach { tl =>
|
||||
tl.a.ready := Bool(true)
|
||||
tl.b.valid := Bool(false)
|
||||
tl.c.ready := Bool(true)
|
||||
tl.d.valid := Bool(false)
|
||||
tl.e.ready := Bool(true)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
trait PeripheryMasterTLMMIOModule {
|
||||
this: HasTopLevelNetworksModule {
|
||||
val outer: PeripheryMasterTLMMIO
|
||||
val io: PeripheryMasterTLMMIOBundle
|
||||
} =>
|
||||
// nothing to do
|
||||
/** Actually generates the corresponding IO in the concrete Module */
|
||||
trait HasPeripheryMasterTLMMIOPortModuleImp extends LazyMultiIOModuleImp with HasPeripheryMasterTLMMIOPortBundle {
|
||||
val outer: HasPeripheryMasterTLMMIOPort
|
||||
val mmio_tl = IO(outer.mmio_tl.bundleOut)
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
// NOTE: this port is NOT allowed to issue Acquires
|
||||
trait PeripherySlaveTL extends HasTopLevelNetworks {
|
||||
/** Adds an AXI4 port to the system intended to be a slave on an MMIO device bus.
|
||||
* NOTE: this port is NOT allowed to issue Acquires.
|
||||
*/
|
||||
trait HasPeripherySlaveTLPort extends HasSystemNetworks {
|
||||
private val config = p(ExtIn)
|
||||
val l2FrontendTLNode = TLBlindInputNode(Seq(TLClientPortParameters(
|
||||
clients = Seq(TLClientParameters(
|
||||
@@ -321,105 +306,58 @@ trait PeripherySlaveTL extends HasTopLevelNetworks {
|
||||
l2FrontendTLNode))
|
||||
}
|
||||
|
||||
trait PeripherySlaveTLBundle extends HasTopLevelNetworksBundle {
|
||||
val outer: PeripherySlaveTL
|
||||
val l2_frontend_bus_tl = outer.l2FrontendTLNode.bundleIn
|
||||
/** Common io name and methods for propagating or tying off the port bundle */
|
||||
trait HasPeripherySlaveTLPortBundle extends HasPeripheryParameters {
|
||||
val l2_frontend_bus_tl: HeterogeneousBag[TLBundle]
|
||||
def tieOffSlaveTLPort(dummy: Int = 1) {
|
||||
l2_frontend_bus_tl.foreach { tl =>
|
||||
tl.a.valid := Bool(false)
|
||||
tl.b.ready := Bool(true)
|
||||
tl.c.valid := Bool(false)
|
||||
tl.d.ready := Bool(true)
|
||||
tl.e.valid := Bool(false)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
trait PeripherySlaveTLModule extends HasTopLevelNetworksModule {
|
||||
val outer: PeripherySlaveTL
|
||||
val io: PeripherySlaveTLBundle
|
||||
// nothing to do
|
||||
/** Actually generates the corresponding IO in the concrete Module */
|
||||
trait HasPeripherySlaveTLPortModuleImp extends LazyMultiIOModuleImp with HasPeripherySlaveTLPortBundle {
|
||||
val outer: HasPeripherySlaveTLPort
|
||||
val l2_frontend_bus_tl = IO(outer.l2FrontendTLNode.bundleIn)
|
||||
}
|
||||
|
||||
/////
|
||||
///// The following traits add specific devices to the periphery of the system.
|
||||
|
||||
trait PeripheryBootROM {
|
||||
this: HasTopLevelNetworks =>
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
/** Adds a /dev/null slave that generates */
|
||||
trait HasPeripheryZeroSlave extends HasSystemNetworks {
|
||||
private val config = p(ZeroConfig)
|
||||
private val address = AddressSet(config.base, config.size-1)
|
||||
private val blockBytes = p(CacheBlockBytes)
|
||||
|
||||
private val bootrom_address = 0x10000
|
||||
private val bootrom_size = 0x10000
|
||||
private lazy val bootrom_contents = GenerateBootROM(coreplex.dtb)
|
||||
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
|
||||
bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
|
||||
val zeros = mem map { case xbar =>
|
||||
val zero = LazyModule(new TLZero(address, beatBytes = config.beatBytes))
|
||||
zero.node := TLFragmenter(config.beatBytes, blockBytes)(xbar.node)
|
||||
zero
|
||||
}
|
||||
}
|
||||
|
||||
trait PeripheryBootROMBundle {
|
||||
this: HasTopLevelNetworksBundle {
|
||||
val outer: PeripheryBootROM
|
||||
} =>
|
||||
}
|
||||
|
||||
trait PeripheryBootROMModule {
|
||||
this: HasTopLevelNetworksModule {
|
||||
val outer: PeripheryBootROM
|
||||
val io: PeripheryBootROMBundle
|
||||
} =>
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
trait PeripheryTestRAM {
|
||||
this: HasTopLevelNetworks =>
|
||||
|
||||
val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, peripheryBusConfig.beatBytes))
|
||||
testram.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
|
||||
}
|
||||
|
||||
trait PeripheryTestRAMBundle {
|
||||
this: HasTopLevelNetworksBundle {
|
||||
val outer: PeripheryTestRAM
|
||||
} =>
|
||||
}
|
||||
|
||||
trait PeripheryTestRAMModule {
|
||||
this: HasTopLevelNetworksModule {
|
||||
val outer: PeripheryTestRAM
|
||||
val io: PeripheryTestRAMBundle
|
||||
} =>
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
trait PeripheryTestBusMaster {
|
||||
this: HasTopLevelNetworks =>
|
||||
val fuzzer = LazyModule(new TLFuzzer(5000))
|
||||
peripheryBus.node := fuzzer.node
|
||||
}
|
||||
|
||||
trait PeripheryTestBusMasterBundle {
|
||||
this: HasTopLevelNetworksBundle {
|
||||
val outer: PeripheryTestBusMaster
|
||||
} =>
|
||||
}
|
||||
|
||||
trait PeripheryTestBusMasterModule {
|
||||
this: HasTopLevelNetworksModule {
|
||||
val outer: PeripheryTestBusMaster
|
||||
val io: PeripheryTestBusMasterBundle
|
||||
} =>
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
trait PeripheryErrorSlave {
|
||||
this: HasTopLevelNetworks =>
|
||||
/** Adds a /dev/null slave that generates TL2 error response messages. */
|
||||
trait HasPeripheryErrorSlave extends HasSystemNetworks {
|
||||
private val config = p(ErrorConfig)
|
||||
private val maxXfer = min(config.address.map(_.alignment).max.toInt, 4096)
|
||||
val error = LazyModule(new TLError(config.address, peripheryBusConfig.beatBytes))
|
||||
error.node := TLFragmenter(peripheryBusConfig.beatBytes, maxXfer)(peripheryBus.node)
|
||||
}
|
||||
|
||||
trait PeripheryErrorSlaveBundle {
|
||||
this: HasTopLevelNetworksBundle {
|
||||
val outer: PeripheryErrorSlave
|
||||
} =>
|
||||
|
||||
/** Adds a SRAM to the system for testing purposes. */
|
||||
trait HasPeripheryTestRAMSlave extends HasSystemNetworks {
|
||||
val testram = LazyModule(new TLRAM(AddressSet(0x52000000, 0xfff), true, peripheryBusConfig.beatBytes))
|
||||
testram.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
|
||||
}
|
||||
|
||||
trait PeripheryErrorSlaveModule {
|
||||
this: HasTopLevelNetworksModule {
|
||||
val outer: PeripheryErrorSlave
|
||||
val io: PeripheryErrorSlaveBundle
|
||||
} =>
|
||||
/** Adds a fuzzing master to the system for testing purposes. */
|
||||
trait HasPeripheryTestFuzzMaster extends HasSystemNetworks {
|
||||
val fuzzer = LazyModule(new TLFuzzer(5000))
|
||||
peripheryBus.node := fuzzer.node
|
||||
}
|
||||
|
||||
@@ -4,153 +4,112 @@ package rocketchip
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import coreplex._
|
||||
import diplomacy._
|
||||
import jtag.JTAGIO
|
||||
import uncore.tilelink2._
|
||||
import uncore.devices._
|
||||
import util._
|
||||
import jtag.JTAGIO
|
||||
import coreplex._
|
||||
|
||||
// System with JTAG DTM Instantiated inside. JTAG interface is
|
||||
// exported outside.
|
||||
|
||||
trait PeripheryJTAGDTM extends HasTopLevelNetworks {
|
||||
val module: PeripheryJTAGDTMModule
|
||||
/** All the traits defined in this file assume that they are being mixed in
|
||||
* to a system that has a standard RISCV-based coreplex platform.
|
||||
*/
|
||||
trait HasCoreplexRISCVPlatform {
|
||||
implicit val p: Parameters
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
}
|
||||
|
||||
trait PeripheryJTAGDTMBundle extends HasTopLevelNetworksBundle {
|
||||
val outer: PeripheryJTAGDTM
|
||||
|
||||
/** A wrapper around JTAG providing a reset signal and manufacturer id. */
|
||||
class SystemJTAGIO extends Bundle {
|
||||
val jtag = new JTAGIO(hasTRSTn = false).flip
|
||||
val jtag_reset = Bool(INPUT)
|
||||
val jtag_mfr_id = UInt(INPUT, 11)
|
||||
|
||||
val reset = Bool(INPUT)
|
||||
val mfr_id = UInt(INPUT, 11)
|
||||
}
|
||||
|
||||
trait PeripheryJTAGDTMModule extends HasTopLevelNetworksModule {
|
||||
val outer: PeripheryJTAGDTM
|
||||
val io: PeripheryJTAGDTMBundle
|
||||
|
||||
val dtm = Module (new DebugTransportModuleJTAG(p(DMKey).nDMIAddrSize, p(JtagDTMKey)))
|
||||
dtm.io.jtag <> io.jtag
|
||||
|
||||
dtm.clock := io.jtag.TCK
|
||||
dtm.io.jtag_reset := io.jtag_reset
|
||||
dtm.io.jtag_mfr_id := io.jtag_mfr_id
|
||||
dtm.reset := dtm.io.fsmReset
|
||||
|
||||
outer.coreplex.module.io.debug.dmi <> dtm.io.dmi
|
||||
outer.coreplex.module.io.debug.dmiClock := io.jtag.TCK
|
||||
outer.coreplex.module.io.debug.dmiReset := ResetCatchAndSync(io.jtag.TCK, io.jtag_reset, "dmiResetCatch")
|
||||
|
||||
/** A wrapper bundle containing one of the two possible debug interfaces */
|
||||
class DebugIO(implicit p: Parameters) extends ParameterizedBundle()(p) {
|
||||
val clockeddmi = (!p(IncludeJtagDTM)).option(new ClockedDMIIO().flip)
|
||||
val systemjtag = (p(IncludeJtagDTM)).option(new SystemJTAGIO)
|
||||
val ndreset = Bool(OUTPUT)
|
||||
val dmactive = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
// System with Debug Module Interface Only. Any sort of DTM
|
||||
// can be connected outside. DMI Clock and Reset must be provided.
|
||||
|
||||
trait PeripheryDMI extends HasTopLevelNetworks {
|
||||
val module: PeripheryDMIModule
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
/** Either adds a JTAG DTM to system, and exports a JTAG interface,
|
||||
* or exports the Debug Module Interface (DMI), based on a global parameter.
|
||||
*/
|
||||
trait HasPeripheryDebug extends HasSystemNetworks with HasCoreplexRISCVPlatform {
|
||||
val module: HasPeripheryDebugModuleImp
|
||||
}
|
||||
|
||||
trait PeripheryDMIBundle extends HasTopLevelNetworksBundle {
|
||||
val outer: PeripheryDMI
|
||||
|
||||
val debug = new ClockedDMIIO().flip
|
||||
trait HasPeripheryDebugBundle extends HasPeripheryParameters {
|
||||
val debug: DebugIO
|
||||
def connectDebug(c: Clock, r: Bool, out: Bool) {
|
||||
debug.clockeddmi.foreach { d =>
|
||||
val dtm = Module(new SimDTM).connect(c, r, d, out)
|
||||
}
|
||||
debug.systemjtag.foreach { sj =>
|
||||
val jtag = Module(new JTAGVPI).connect(sj.jtag, sj.reset, r, out)
|
||||
sj.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
trait PeripheryDMIModule extends HasTopLevelNetworksModule {
|
||||
val outer: PeripheryDMI
|
||||
val io: PeripheryDMIBundle
|
||||
trait HasPeripheryDebugModuleImp extends LazyMultiIOModuleImp with HasPeripheryDebugBundle {
|
||||
val outer: HasPeripheryDebug
|
||||
|
||||
outer.coreplex.module.io.debug <> io.debug
|
||||
}
|
||||
val debug = IO(new DebugIO)
|
||||
|
||||
// System with DMI or JTAG interface based on a parameter
|
||||
debug.clockeddmi.foreach { dbg => outer.coreplex.module.io.debug <> dbg }
|
||||
|
||||
trait PeripheryDebug extends HasTopLevelNetworks {
|
||||
val module: PeripheryDebugModule
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
}
|
||||
val dtm = debug.systemjtag.map { sj =>
|
||||
val dtm = Module(new DebugTransportModuleJTAG(p(DMKey).nDMIAddrSize, p(JtagDTMKey)))
|
||||
dtm.io.jtag <> sj.jtag
|
||||
|
||||
trait PeripheryDebugBundle extends HasTopLevelNetworksBundle {
|
||||
val outer: PeripheryDebug
|
||||
|
||||
val debug = (!p(IncludeJtagDTM)).option(new ClockedDMIIO().flip)
|
||||
|
||||
val jtag = (p(IncludeJtagDTM)).option(new JTAGIO(hasTRSTn = false).flip)
|
||||
val jtag_reset = (p(IncludeJtagDTM)).option(Bool(INPUT))
|
||||
val jtag_mfr_id = (p(IncludeJtagDTM)).option(UInt(INPUT, 11))
|
||||
|
||||
val ndreset = Bool(OUTPUT)
|
||||
val dmactive = Bool(OUTPUT)
|
||||
}
|
||||
|
||||
trait PeripheryDebugModule extends HasTopLevelNetworksModule {
|
||||
val outer: PeripheryDebug
|
||||
val io: PeripheryDebugBundle
|
||||
|
||||
io.debug.foreach { dbg => outer.coreplex.module.io.debug <> dbg }
|
||||
|
||||
val dtm = if (io.jtag.isDefined) Some[DebugTransportModuleJTAG](Module (new DebugTransportModuleJTAG(p(DMKey).nDMIAddrSize, p(JtagDTMKey)))) else None
|
||||
dtm.foreach { dtm =>
|
||||
dtm.io.jtag <> io.jtag.get
|
||||
|
||||
dtm.clock := io.jtag.get.TCK
|
||||
dtm.io.jtag_reset := io.jtag_reset.get
|
||||
dtm.io.jtag_mfr_id := io.jtag_mfr_id.get
|
||||
dtm.clock := sj.jtag.TCK
|
||||
dtm.io.jtag_reset := sj.reset
|
||||
dtm.io.jtag_mfr_id := sj.mfr_id
|
||||
dtm.reset := dtm.io.fsmReset
|
||||
|
||||
outer.coreplex.module.io.debug.dmi <> dtm.io.dmi
|
||||
outer.coreplex.module.io.debug.dmiClock := io.jtag.get.TCK
|
||||
outer.coreplex.module.io.debug.dmiReset := ResetCatchAndSync(io.jtag.get.TCK, io.jtag_reset.get, "dmiResetCatch")
|
||||
outer.coreplex.module.io.debug.dmiClock := sj.jtag.TCK
|
||||
outer.coreplex.module.io.debug.dmiReset := ResetCatchAndSync(sj.jtag.TCK, sj.reset, "dmiResetCatch")
|
||||
dtm
|
||||
}
|
||||
|
||||
io.ndreset := outer.coreplex.module.io.ndreset
|
||||
io.dmactive := outer.coreplex.module.io.dmactive
|
||||
|
||||
debug.ndreset := outer.coreplex.module.io.ndreset
|
||||
debug.dmactive := outer.coreplex.module.io.dmactive
|
||||
}
|
||||
|
||||
/// Real-time clock is based on RTCPeriod relative to Top clock
|
||||
|
||||
trait PeripheryCounter extends HasTopLevelNetworks {
|
||||
val module: PeripheryCounterModule
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
/** Real-time clock is based on RTCPeriod relative to system clock.
|
||||
* Note: nothing about this is diplomatic, all the work is done in the ModuleImp
|
||||
*/
|
||||
trait HasPeripheryRTCCounter extends HasSystemNetworks with HasCoreplexRISCVPlatform {
|
||||
val module: HasPeripheryRTCCounterModuleImp
|
||||
}
|
||||
|
||||
trait PeripheryCounterBundle extends HasTopLevelNetworksBundle {
|
||||
val outer: PeripheryCounter
|
||||
trait HasPeripheryRTCCounterModuleImp extends LazyMultiIOModuleImp {
|
||||
val outer: HasPeripheryRTCCounter
|
||||
val period = p(rocketchip.RTCPeriod)
|
||||
val rtcCounter = RegInit(UInt(0, width = log2Up(period)))
|
||||
val rtcWrap = rtcCounter === UInt(period-1)
|
||||
|
||||
rtcCounter := Mux(rtcWrap, UInt(0), rtcCounter + UInt(1))
|
||||
outer.coreplex.module.io.rtcToggle := rtcCounter(log2Up(period)-1)
|
||||
}
|
||||
|
||||
trait PeripheryCounterModule extends HasTopLevelNetworksModule {
|
||||
val outer: PeripheryCounter
|
||||
val io: PeripheryCounterBundle
|
||||
/** Adds a boot ROM that contains the DTB describing the system's coreplex. */
|
||||
trait HasPeripheryBootROM extends HasSystemNetworks with HasCoreplexRISCVPlatform {
|
||||
val bootrom_address = 0x10000
|
||||
val bootrom_size = 0x10000
|
||||
val bootrom_hang = 0x10040
|
||||
private lazy val bootrom_contents = GenerateBootROM(coreplex.dtb)
|
||||
val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
|
||||
|
||||
{
|
||||
val period = p(rocketchip.RTCPeriod)
|
||||
val rtcCounter = RegInit(UInt(0, width = log2Up(period)))
|
||||
val rtcWrap = rtcCounter === UInt(period-1)
|
||||
rtcCounter := Mux(rtcWrap, UInt(0), rtcCounter + UInt(1))
|
||||
|
||||
outer.coreplex.module.io.rtcToggle := rtcCounter(log2Up(period)-1)
|
||||
}
|
||||
bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
|
||||
}
|
||||
|
||||
/// Coreplex will power-on running at 0x1000 (BootROM)
|
||||
|
||||
trait HardwiredResetVector extends HasTopLevelNetworks {
|
||||
val module: HardwiredResetVectorModule
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
}
|
||||
|
||||
trait HardwiredResetVectorBundle extends HasTopLevelNetworksBundle {
|
||||
val outer: HardwiredResetVector
|
||||
}
|
||||
|
||||
trait HardwiredResetVectorModule extends HasTopLevelNetworksModule {
|
||||
val outer: HardwiredResetVector
|
||||
val io: HardwiredResetVectorBundle
|
||||
|
||||
outer.coreplex.module.io.resetVector := UInt(0x10040) // boot ROM: hang
|
||||
/** Coreplex will power-on running at 0x10040 (BootROM) */
|
||||
trait HasPeripheryBootROMModuleImp extends LazyMultiIOModuleImp {
|
||||
val outer: HasPeripheryBootROM
|
||||
outer.coreplex.module.io.resetVector := UInt(outer.bootrom_hang)
|
||||
}
|
||||
|
||||
@@ -4,10 +4,11 @@ package rocketchip
|
||||
|
||||
import Chisel._
|
||||
import coreplex.RocketPlex
|
||||
import diplomacy.LazyModule
|
||||
import diplomacy.{LazyModule, LazyMultiIOModuleImp}
|
||||
|
||||
trait RocketPlexMaster extends HasTopLevelNetworks {
|
||||
val module: RocketPlexMasterModule
|
||||
/** Add a RocketPlex to the system */
|
||||
trait HasRocketPlexMaster extends HasSystemNetworks with HasCoreplexRISCVPlatform {
|
||||
val module: HasRocketPlexMasterModuleImp
|
||||
|
||||
val coreplex = LazyModule(new RocketPlex)
|
||||
|
||||
@@ -20,15 +21,9 @@ trait RocketPlexMaster extends HasTopLevelNetworks {
|
||||
(mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel }
|
||||
}
|
||||
|
||||
trait RocketPlexMasterBundle extends HasTopLevelNetworksBundle {
|
||||
val outer: RocketPlexMaster
|
||||
}
|
||||
|
||||
trait RocketPlexMasterModule extends HasTopLevelNetworksModule {
|
||||
val outer: RocketPlexMaster
|
||||
val io: RocketPlexMasterBundle
|
||||
val clock: Clock
|
||||
val reset: Bool
|
||||
trait HasRocketPlexMasterModuleImp extends LazyMultiIOModuleImp {
|
||||
val outer: HasRocketPlexMaster
|
||||
|
||||
outer.coreplex.module.io.tcrs.foreach { case tcr =>
|
||||
tcr.clock := clock
|
||||
|
||||
24
src/main/scala/rocketchip/System.scala
Normal file
24
src/main/scala/rocketchip/System.scala
Normal file
@@ -0,0 +1,24 @@
|
||||
// See LICENSE.SiFive for license details.
|
||||
|
||||
package rocketchip
|
||||
|
||||
import Chisel._
|
||||
import config.Parameters
|
||||
import diplomacy._
|
||||
import util._
|
||||
|
||||
/** BareSystem is the root class for creating a top-level RTL module */
|
||||
abstract class BareSystem(implicit p: Parameters) extends LazyModule {
|
||||
ElaborationArtefacts.add("graphml", graphML)
|
||||
}
|
||||
|
||||
abstract class BareSystemModule[+L <: BareSystem](_outer: L) extends LazyMultiIOModuleImp(_outer) {
|
||||
val outer = _outer
|
||||
}
|
||||
|
||||
/** Base System class with no peripheral devices or ports added */
|
||||
abstract class BaseSystem(implicit p: Parameters) extends BareSystem with HasSystemNetworks {
|
||||
override val module: BaseSystemModule[BaseSystem]
|
||||
}
|
||||
|
||||
abstract class BaseSystemModule[+L <: BaseSystem](_outer: L) extends BareSystemModule(_outer)
|
||||
@@ -16,30 +16,13 @@ class TestHarness()(implicit p: Parameters) extends Module {
|
||||
}
|
||||
|
||||
val dut = Module(LazyModule(new ExampleRocketTop).module)
|
||||
dut.reset := reset | dut.io.ndreset
|
||||
dut.reset := reset | dut.debug.ndreset
|
||||
|
||||
|
||||
dut.io.interrupts := UInt(0)
|
||||
|
||||
val channels = p(coreplex.BankedL2Config).nMemoryChannels
|
||||
if (channels > 0) Module(LazyModule(new SimAXIMem(channels)).module).io.axi4 <> dut.io.mem_axi4
|
||||
|
||||
if (!p(IncludeJtagDTM)) {
|
||||
val dtm = Module(new SimDTM).connect(clock, reset, dut.io.debug.get, io.success)
|
||||
} else {
|
||||
val jtag = Module(new JTAGVPI).connect(dut.io.jtag.get, dut.io.jtag_reset.get, reset, io.success)
|
||||
dut.io.jtag_mfr_id.get := p(JtagDTMKey).idcodeManufId.U(11.W)
|
||||
}
|
||||
|
||||
val mmio_sim = Module(LazyModule(new SimAXIMem(1, 4096)).module)
|
||||
mmio_sim.io.axi4 <> dut.io.mmio_axi4
|
||||
|
||||
val l2_axi4 = dut.io.l2_frontend_bus_axi4(0)
|
||||
l2_axi4.ar.valid := Bool(false)
|
||||
l2_axi4.aw.valid := Bool(false)
|
||||
l2_axi4.w .valid := Bool(false)
|
||||
l2_axi4.r .ready := Bool(true)
|
||||
l2_axi4.b .ready := Bool(true)
|
||||
dut.tieOffInterrupts()
|
||||
dut.connectSimAXIMem()
|
||||
dut.connectSimAXIMMIO()
|
||||
dut.tieOffAXI4SlavePort()
|
||||
dut.connectDebug(clock, reset, io.success)
|
||||
}
|
||||
|
||||
class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) extends LazyModule {
|
||||
|
||||
Reference in New Issue
Block a user