riscv/rocket-chip
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rocketchip: top-level systems are now multi-IO modules

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Cake pattern only 2 layers instead of 3.
Standardized naming convention.
Comments for periphery mix-ins.
Testharnesses use new periphery helper methods.
This commit is contained in:
Henry Cook
2017-06-01 16:06:36 -07:00
parent 2e8a40a23f
commit 9bbde9767c
9 changed files with 303 additions and 505 deletions
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11
src/main/scala/groundtest/TestHarness.scala
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@ -9,13 +9,8 @@ import rocketchip._
import util._
class TestHarness(implicit p: Parameters) extends Module {
val io = new Bundle {
val success = Bool(OUTPUT)
}
val io = new Bundle { val success = Bool(OUTPUT) }
val dut = Module(LazyModule(new GroundTestTop).module)
io.success := dut.io.success
val channels = p(coreplex.BankedL2Config).nMemoryChannels
if (channels > 0) Module(LazyModule(new SimAXIMem(channels)).module).io.axi4 <> dut.io.mem_axi4
io.success := dut.io_success
dut.connectSimAXIMem()
}

27
src/main/scala/groundtest/Top.scala
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@ -3,15 +3,14 @@
package groundtest
import Chisel._
import config._
import diplomacy._
import coreplex._
import config.Parameters
import diplomacy.LazyModule
import rocketchip._
class GroundTestTop(implicit p: Parameters) extends BaseTop
with PeripheryMasterAXI4Mem
with PeripheryTestRAM {
override lazy val module = new GroundTestTopModule(this, () => new GroundTestTopBundle(this))
class GroundTestTop(implicit p: Parameters) extends BaseSystem
with HasPeripheryMasterAXI4MemPort
with HasPeripheryTestRAMSlave {
override lazy val module = new GroundTestTopModule(this)
val coreplex = LazyModule(new GroundTestCoreplex)
@ -20,14 +19,8 @@ class GroundTestTop(implicit p: Parameters) extends BaseTop
(mem zip coreplex.mem) foreach { case (xbar, channel) => xbar.node :=* channel }
}
class GroundTestTopBundle[+L <: GroundTestTop](_outer: L) extends BaseTopBundle(_outer)
with PeripheryMasterAXI4MemBundle
with PeripheryTestRAMBundle {
val success = Bool(OUTPUT)
}
class GroundTestTopModule[+L <: GroundTestTop, +B <: GroundTestTopBundle[L]](_outer: L, _io: () => B) extends BaseTopModule(_outer, _io)
with PeripheryMasterAXI4MemModule
with PeripheryTestRAMModule {
io.success := outer.coreplex.module.io.success
class GroundTestTopModule[+L <: GroundTestTop](_outer: L) extends BaseSystemModule(_outer)
with HasPeripheryMasterAXI4MemPortModuleImp {
val io_success = IO(Bool(OUTPUT))
io_success := outer.coreplex.module.io.success
}