riscv/rocket-chip
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WIP on FPU

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This commit is contained in:
Andrew Waterman 2012-02-12 04:36:01 -08:00
parent 50a283d311
commit 9bb1558a34
4 changed files with 202 additions and 95 deletions
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4
rocket/src/main/scala/cpu.scala
View File

@ -116,10 +116,8 @@ class rocketProc extends Component
if (HAVE_FPU)
{
val fpu = new rocketFPU
fpu.io.dmem.resp_val := arb.io.cpu.resp_val;
fpu.io.dmem.resp_tag := arb.io.cpu.resp_tag;
fpu.io.dmem.resp_data := arb.io.cpu.resp_data;
dpath.io.fpu <> fpu.io.dpath
ctrl.io.fpu <> fpu.io.ctrl
}
ctrl.io.ext_mem.req_val := Bool(false)

66
rocket/src/main/scala/ctrl.scala
View File

@ -37,6 +37,7 @@ class ioCtrlDpath extends Bundle()
val mem_load = Bool(OUTPUT);
val ex_ext_mem_val = Bool(OUTPUT);
val ex_fp_val= Bool(OUTPUT);
val mem_fp_val= Bool(OUTPUT);
val ex_wen = Bool(OUTPUT);
val mem_wen = Bool(OUTPUT);
val wb_wen = Bool(OUTPUT);
@ -90,15 +91,13 @@ class ioCtrlAll extends Bundle()
val xcpt_itlb = Bool(INPUT);
val xcpt_ma_ld = Bool(INPUT);
val xcpt_ma_st = Bool(INPUT);
val fpu = new ioCtrlFPU();
}
class rocketCtrl extends Component
{
val io = new ioCtrlAll();
val fpdec = new rocketFPUDecoder
fpdec.io.inst := io.dpath.inst
val xpr64 = Y;
val cs =
ListLookup(io.dpath.inst,
@ -212,12 +211,12 @@ class rocketCtrl extends Component
// Instructions that have not yet been implemented
// Faking these for now so akaros will boot
//MFFSR-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
//MTFSR-> List(Y, N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FLW-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FLD-> List(Y, N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FSW-> List(Y, N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FSD-> List(Y, N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
MFFSR-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
MTFSR-> List(FPU_Y,N,BR_N, REN_N,REN_N,A2_X, DW_X, FN_X, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_X, REN_N,WEN_N,I_X ,SYNC_N,N,N,N,Y),
FLW-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FLD-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_ITYPE,DW_XPR,FN_ADD, M_Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FSW-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
FSD-> List(FPU_Y,N,BR_N, REN_N,REN_Y,A2_BTYPE,DW_XPR,FN_ADD, M_Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, WEN_N,WA_X, WB_ALU,REN_N,WEN_N,I_X ,SYNC_N,N,N,N,N),
// Vector Stuff
VVCFGIVL-> List(VEC_Y,Y,BR_N, REN_N,REN_Y,A2_ZERO, DW_XPR,FN_ADD, M_N,M_X, MT_X, N,MUL_X, N,DIV_X, WEN_Y,WA_RD,WB_ALU,REN_N,WEN_N,I_X, SYNC_N,N,N,N,Y),
@ -322,6 +321,7 @@ class rocketCtrl extends Component
val mem_reg_xcpt_fpu = Reg(resetVal = Bool(false));
val mem_reg_xcpt_vec = Reg(resetVal = Bool(false));
val mem_reg_xcpt_syscall = Reg(resetVal = Bool(false));
val mem_reg_fp_val = Reg(resetVal = Bool(false));
val mem_reg_replay = Reg(resetVal = Bool(false));
val mem_reg_kill = Reg(resetVal = Bool(false));
val mem_reg_ext_mem_val = Reg(resetVal = Bool(false))
@ -355,7 +355,7 @@ class rocketCtrl extends Component
// executing ERET when traps are enabled causes an illegal instruction exception (as per ISA sim)
val illegal_inst =
!(id_int_val.toBool || fpdec.io.valid || id_vec_val.toBool) ||
!(id_int_val.toBool || io.fpu.dec.valid || id_vec_val.toBool) ||
(id_eret.toBool && io.dpath.status(SR_ET).toBool);
when (reset.toBool || io.dpath.killd) {
@ -388,7 +388,7 @@ class rocketCtrl extends Component
ex_reg_mul_val := id_mul_val.toBool && id_waddr != UFix(0);
ex_reg_mem_val := id_mem_val.toBool;
ex_reg_wen := id_wen.toBool && id_waddr != UFix(0);
ex_reg_fp_wen := fpdec.io.wen;
ex_reg_fp_wen := io.fpu.dec.wen;
ex_reg_eret := id_eret.toBool;
ex_reg_replay_next := id_replay_next.toBool;
ex_reg_inst_di := (id_irq === I_DI);
@ -399,7 +399,7 @@ class rocketCtrl extends Component
ex_reg_xcpt_illegal := illegal_inst;
ex_reg_xcpt_privileged := (id_privileged & ~io.dpath.status(SR_S)).toBool;
ex_reg_xcpt_syscall := id_syscall.toBool;
ex_reg_fp_val := fpdec.io.valid;
ex_reg_fp_val := io.fpu.dec.valid;
ex_reg_vec_val := id_vec_val.toBool
ex_reg_replay := id_reg_replay || ex_reg_replay_next;
ex_reg_load_use := id_load_use;
@ -447,6 +447,7 @@ class rocketCtrl extends Component
mem_reg_xcpt_fpu := Bool(false);
mem_reg_xcpt_vec := Bool(false);
mem_reg_xcpt_syscall := Bool(false);
mem_reg_fp_val := Bool(false);
}
.otherwise {
mem_reg_div_mul_val := ex_reg_div_val || ex_reg_mul_val;
@ -464,6 +465,7 @@ class rocketCtrl extends Component
mem_reg_xcpt_fpu := ex_reg_fp_val && !io.dpath.status(SR_EF).toBool;
mem_reg_xcpt_vec := ex_reg_vec_val && !io.dpath.status(SR_EV).toBool;
mem_reg_xcpt_syscall := ex_reg_xcpt_syscall;
mem_reg_fp_val := ex_reg_fp_val
}
mem_reg_ext_mem_val := ex_reg_ext_mem_val;
mem_reg_mem_cmd := ex_reg_mem_cmd;
@ -518,10 +520,10 @@ class rocketCtrl extends Component
fp_sboard.io.clr := io.dpath.fp_sboard_clr;
fp_sboard.io.clra := io.dpath.fp_sboard_clra;
id_stall_fpu = fpdec.io.ren1 && fp_sboard.io.stalla ||
fpdec.io.ren2 && fp_sboard.io.stallb ||
fpdec.io.ren3 && fp_sboard.io.stallc ||
fpdec.io.wen && fp_sboard.io.stalld
id_stall_fpu = io.fpu.dec.ren1 && fp_sboard.io.stalla ||
io.fpu.dec.ren2 && fp_sboard.io.stallb ||
io.fpu.dec.ren3 && fp_sboard.io.stallc ||
io.fpu.dec.wen && fp_sboard.io.stalld
}
// exception handling
@ -589,7 +591,8 @@ class rocketCtrl extends Component
val replay_ex = wb_reg_dcache_miss && ex_reg_load_use || mem_reg_flush_inst ||
ex_reg_replay || ex_reg_mem_val && !(io.dmem.req_rdy && io.dtlb_rdy) ||
ex_reg_div_val && !io.dpath.div_rdy ||
ex_reg_mul_val && !io.dpath.mul_rdy
ex_reg_mul_val && !io.dpath.mul_rdy ||
io.fpu.nack
val kill_ex = take_pc_wb || replay_ex
mem_reg_replay := replay_ex && !take_pc_wb;
@ -627,10 +630,10 @@ class rocketCtrl extends Component
id_renx2.toBool && id_raddr2 === io.dpath.ex_waddr ||
id_wen.toBool && id_waddr === io.dpath.ex_waddr)
val fp_data_hazard_ex = ex_reg_fp_wen &&
(fpdec.io.ren1 && id_raddr1 === io.dpath.ex_waddr ||
fpdec.io.ren2 && id_raddr2 === io.dpath.ex_waddr ||
fpdec.io.ren3 && id_raddr3 === io.dpath.ex_waddr ||
fpdec.io.wen && id_waddr === io.dpath.ex_waddr)
(io.fpu.dec.ren1 && id_raddr1 === io.dpath.ex_waddr ||
io.fpu.dec.ren2 && id_raddr2 === io.dpath.ex_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.ex_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr)
val id_ex_hazard = data_hazard_ex && (ex_reg_mem_val || ex_reg_div_val || ex_reg_mul_val) ||
fp_data_hazard_ex && ex_reg_mem_val
@ -643,10 +646,10 @@ class rocketCtrl extends Component
id_renx2.toBool && id_raddr2 === io.dpath.mem_waddr ||
id_wen.toBool && id_waddr === io.dpath.mem_waddr)
val fp_data_hazard_mem = mem_reg_fp_wen &&
(fpdec.io.ren1 && id_raddr1 === io.dpath.mem_waddr ||
fpdec.io.ren2 && id_raddr2 === io.dpath.mem_waddr ||
fpdec.io.ren3 && id_raddr3 === io.dpath.mem_waddr ||
fpdec.io.wen && id_waddr === io.dpath.mem_waddr)
(io.fpu.dec.ren1 && id_raddr1 === io.dpath.mem_waddr ||
io.fpu.dec.ren2 && id_raddr2 === io.dpath.mem_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.mem_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.mem_waddr)
val id_mem_hazard = data_hazard_mem && (mem_reg_mem_val && mem_mem_cmd_bh || mem_reg_div_mul_val)
id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem)
@ -656,10 +659,10 @@ class rocketCtrl extends Component
id_renx2.toBool && id_raddr2 === io.dpath.wb_waddr ||
id_wen.toBool && id_waddr === io.dpath.wb_waddr)
val fp_data_hazard_wb = wb_reg_fp_wen &&
(fpdec.io.ren1 && id_raddr1 === io.dpath.wb_waddr ||
fpdec.io.ren2 && id_raddr2 === io.dpath.wb_waddr ||
fpdec.io.ren3 && id_raddr3 === io.dpath.wb_waddr ||
fpdec.io.wen && id_waddr === io.dpath.wb_waddr)
(io.fpu.dec.ren1 && id_raddr1 === io.dpath.wb_waddr ||
io.fpu.dec.ren2 && id_raddr2 === io.dpath.wb_waddr ||
io.fpu.dec.ren3 && id_raddr3 === io.dpath.wb_waddr ||
io.fpu.dec.wen && id_waddr === io.dpath.wb_waddr)
val id_wb_hazard = data_hazard_wb && (wb_reg_dcache_miss || wb_reg_div_mul_val) ||
fp_data_hazard_wb && wb_reg_dcache_miss
@ -698,6 +701,7 @@ class rocketCtrl extends Component
io.dpath.mul_val := id_mul_val.toBool;
io.dpath.ex_ext_mem_val := ex_reg_ext_mem_val;
io.dpath.ex_fp_val:= ex_reg_fp_val;
io.dpath.mem_fp_val:= mem_reg_fp_val;
io.dpath.ex_wen := ex_reg_wen;
io.dpath.mem_wen := mem_reg_wen;
io.dpath.wb_wen := wb_reg_wen;
@ -711,6 +715,10 @@ class rocketCtrl extends Component
io.dpath.irq_enable := wb_reg_inst_ei;
io.dpath.ex_mem_type := ex_reg_mem_type
io.fpu.valid := !io.dpath.killd && io.fpu.dec.valid
io.fpu.killx := kill_ex
io.fpu.killm := kill_mem
io.dtlb_val := ex_reg_mem_val;
io.dtlb_kill := mem_reg_kill;
io.dmem.req_val := ex_reg_mem_val || ex_reg_ext_mem_val;

12
rocket/src/main/scala/dpath.scala
View File

@ -232,7 +232,8 @@ class rocketDpath extends Component
val id_op2 = Mux(io.ctrl.sel_alu2 === A2_RTYPE, id_rs2, id_imm)
io.ctrl.inst := id_reg_inst;
io.ctrl.inst := id_reg_inst
io.fpu.inst := id_reg_inst
// execute stage
ex_reg_pc := id_reg_pc;
@ -301,7 +302,7 @@ class rocketDpath extends Component
// D$ request interface (registered inside D$ module)
// other signals (req_val, req_rdy) connect to control module
io.dmem.req_addr := ex_effective_address.toUFix;
io.dmem.req_data := (if (HAVE_FPU) Mux(io.ctrl.ex_fp_val, io.fpu.store_data, mem_reg_rs2) else mem_reg_rs2)
io.dmem.req_data := (if (HAVE_FPU) Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2) else mem_reg_rs2)
io.dmem.req_tag := Cat(ex_reg_waddr, io.ctrl.ex_fp_val, io.ctrl.ex_ext_mem_val).toUFix
// processor control regfile read
@ -374,7 +375,7 @@ class rocketDpath extends Component
// 32/64 bit load handling (moved to earlier in file)
// writeback stage
// writeback arbitration
val dmem_resp_ext = io.dmem.resp_tag(0).toBool
val dmem_resp_xpu = !io.dmem.resp_tag(0).toBool && !io.dmem.resp_tag(1).toBool
val dmem_resp_fpu = !io.dmem.resp_tag(0).toBool && io.dmem.resp_tag(1).toBool
@ -394,6 +395,11 @@ class rocketDpath extends Component
mem_reg_wdata))
val mem_ll_wb = dmem_resp_replay || div_result_val || mul_result_val
io.fpu.dmem_resp_val := io.dmem.resp_val && dmem_resp_fpu
io.fpu.dmem_resp_data := io.dmem.resp_data
io.fpu.dmem_resp_tag := dmem_resp_waddr
// writeback stage
wb_reg_pc := mem_reg_pc;
wb_reg_inst := mem_reg_inst
wb_reg_ll_wb := mem_ll_wb

211
rocket/src/main/scala/fpu.scala
View File

@ -1,22 +1,69 @@
package Top
import Chisel._
import Node._;
import Node._
import Constants._
import Instructions._
object rocketFPConstants
{
val FCMD_ADD = Bits("b000000")
val FCMD_SUB = Bits("b000001")
val FCMD_MUL = Bits("b000010")
val FCMD_DIV = Bits("b000011")
val FCMD_SQRT = Bits("b000100")
val FCMD_SGNINJ = Bits("b000101")
val FCMD_SGNINJN = Bits("b000110")
val FCMD_SGNMUL = Bits("b000111")
val FCMD_TRUNC_L = Bits("b001000")
val FCMD_TRUNCU_L = Bits("b001001")
val FCMD_TRUNC_W = Bits("b001010")
val FCMD_TRUNCU_W = Bits("b001011")
val FCMD_CVT_L = Bits("b001100")
val FCMD_CVTU_L = Bits("b001101")
val FCMD_CVT_W = Bits("b001110")
val FCMD_CVTU_W = Bits("b001111")
val FCMD_CVT_S = Bits("b010000")
val FCMD_CVT_D = Bits("b010001")
val FCMD_C_EQ = Bits("b010101")
val FCMD_C_LT = Bits("b010110")
val FCMD_C_LE = Bits("b010111")
val FCMD_MIN = Bits("b011000")
val FCMD_MAX = Bits("b011001")
val FCMD_MF = Bits("b011100")
val FCMD_MFFSR = Bits("b011101")
val FCMD_MT = Bits("b011110")
val FCMD_MTFSR = Bits("b011111")
val FCMD_MADD = Bits("b100100")
val FCMD_MSUB = Bits("b100101")
val FCMD_NMSUB = Bits("b100110")
val FCMD_NMADD = Bits("b100111")
val FCMD_LOAD = Bits("b111000")
val FCMD_STORE = Bits("b111001")
val FCMD_WIDTH = 6
}
import rocketFPConstants._
class rocketFPUCtrlSigs extends Bundle
{
val cmd = Bits(width = FCMD_WIDTH)
val valid = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val single = Bool()
val fromint = Bool()
val toint = Bool()
val store = Bool()
val fsr = Bool()
}
class rocketFPUDecoder extends Component
{
val io = new Bundle {
val inst = Bits(32, INPUT)
val valid = Bool(OUTPUT)
val wen = Bool(OUTPUT)
val ren1 = Bool(OUTPUT)
val ren2 = Bool(OUTPUT)
val ren3 = Bool(OUTPUT)
val fromint = Bool(OUTPUT)
val toint = Bool(OUTPUT)
val store = Bool(OUTPUT)
val sigs = new rocketFPUCtrlSigs().asOutput
}
// val fp =
// ListLookup(io.dpath.inst,
@ -91,85 +138,133 @@ class rocketFPUDecoder extends Component
val N = Bool(false)
val Y = Bool(true)
val X = Bool(false)
val FCMD_X = FCMD_ADD
val decoder = ListLookup(io.inst,
List (N,X,X,X,X,X,X,X,X),
Array(FLW -> List(Y,Y,N,N,N,Y,N,N,N),
FLD -> List(Y,Y,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,N,N,Y),
FSD -> List(Y,N,N,Y,N,N,N,N,Y),
MTFSR -> List(Y,N,N,N,N,X,N,Y,N),
MFFSR -> List(Y,N,N,N,N,X,N,Y,N)
List (N,FCMD_X, X,X,X,X,X,X,X,X,X),
Array(FLW -> List(Y,FCMD_LOAD, Y,N,N,N,Y,N,N,N,N),
FLD -> List(Y,FCMD_LOAD, Y,N,N,N,N,N,N,N,N),
FSW -> List(Y,FCMD_STORE, N,N,Y,N,Y,N,N,Y,N),
FSD -> List(Y,FCMD_STORE, N,N,Y,N,N,N,N,Y,N),
MTFSR -> List(Y,FCMD_MTFSR, N,N,N,N,X,N,Y,N,Y),
MFFSR -> List(Y,FCMD_MFFSR, N,N,N,N,X,N,Y,N,Y)
))
val valid :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: store :: Nil = decoder
val valid :: cmd :: wen :: ren1 :: ren2 :: ren3 :: single :: fromint :: toint :: store :: fsr :: Nil = decoder
io.valid := valid.toBool
io.wen := wen.toBool
io.ren1 := ren1.toBool
io.ren2 := ren2.toBool
io.ren3 := ren3.toBool
io.single := single.toBool
io.fromint := fromint.toBool
io.toint := toint.toBool
io.store := store.toBool
io.sigs.valid := valid.toBool
io.sigs.cmd := cmd
io.sigs.wen := wen.toBool
io.sigs.ren1 := ren1.toBool
io.sigs.ren2 := ren2.toBool
io.sigs.ren3 := ren3.toBool
io.sigs.single := single.toBool
io.sigs.fromint := fromint.toBool
io.sigs.toint := toint.toBool
io.sigs.store := store.toBool
io.sigs.fsr := fsr.toBool
}
class ioDpathFPU extends Bundle {
val inst = Bits(32, OUTPUT)
val store_data = Bits(64, INPUT)
val dmem_resp_val = Bool(OUTPUT)
val dmem_resp_tag = UFix(5, OUTPUT)
val dmem_resp_data = Bits(64, OUTPUT)
}
class ioCtrlFPU extends Bundle {
val valid = Bool(OUTPUT)
val nack = Bool(INPUT)
val killx = Bool(OUTPUT)
val killm = Bool(OUTPUT)
val dec = new rocketFPUCtrlSigs().asInput
}
class rocketFPIntUnit extends Component
{
val io = new Bundle {
val single = Bool(INPUT)
val cmd = Bits(FCMD_WIDTH, INPUT)
val in = Bits(65, INPUT)
val out = Bits(64, OUTPUT)
}
val unrecoded_s = io.in(31,0)
val unrecoded_d = io.in
val out_s = unrecoded_s
val out_d = unrecoded_d
io.out := Mux(io.single, Cat(out_s, out_s), out_d)
}
class rocketFPU extends Component
{
val io = new Bundle {
val req_valid = Bool(INPUT)
val req_ready = Bool(OUTPUT)
val req_cmd = Bits(6, INPUT)
val req_inst = Bits(32, INPUT)
val killx = Bool(INPUT)
val killm = Bool(INPUT)
val dmem = new ioDmem(List("resp_val", "resp_tag", "resp_data")).flip()
val ctrl = new ioCtrlFPU().flip()
val dpath = new ioDpathFPU().flip()
}
val ex_reg_inst = Reg() { Bits() }
when (io.req_valid) {
ex_reg_inst := io.req_inst
val reg_inst = Reg() { Bits() }
when (io.ctrl.valid) {
reg_inst := io.dpath.inst
}
val reg_valid = Reg(io.ctrl.valid, Bool(false))
val fp_decoder = new rocketFPUDecoder
fp_decoder.io.inst := io.dpath.inst
val ctrl = Reg() { new rocketFPUCtrlSigs }
when (io.ctrl.valid) {
ctrl := fp_decoder.io.sigs
}
val fpdec = new rocketFPUDecoder
fpdec.io.inst := ex_reg_inst
// load response
val dmem_resp_val_fpu = io.dmem.resp_val && io.dmem.resp_tag(0).toBool
val load_wb = Reg(dmem_resp_val_fpu, resetVal = Bool(false))
val load_wb_data = Reg() { Bits() }
val load_wb = Reg(io.dpath.dmem_resp_val, resetVal = Bool(false))
val load_wb_data = Reg() { Bits(width = 64) } // XXX WTF why doesn't bit width inference work for the regfile?!
val load_wb_tag = Reg() { UFix() }
when (dmem_resp_val_fpu) {
load_wb_data := io.dmem.resp_data
load_wb_tag := io.dmem.resp_tag.toUFix >> UFix(1)
when (io.dpath.dmem_resp_val) {
load_wb_data := io.dpath.dmem_resp_data
load_wb_tag := io.dpath.dmem_resp_tag
}
// regfile
val regfile = Mem(32, load_wb_data);
val regfile = Mem(32, load_wb, load_wb_tag, load_wb_data);
regfile.setReadLatency(0);
regfile.setTarget('inst);
regfile.write(load_wb_tag, load_wb_data, load_wb);
io.req_ready := Bool(true)
val ex_rs1 = regfile(ex_reg_inst(16,12))
val ex_rs2 = regfile(ex_reg_inst(21,17))
val ex_rs3 = regfile(ex_reg_inst(26,22))
val ex_rs1 = regfile.read(reg_inst(16,12))
val ex_rs2 = regfile.read(reg_inst(21,17))
val ex_rs3 = regfile.read(reg_inst(26,22))
val fp_toint_data = Reg() { Bits() }
val fp_toint_single = Reg() { Bool() }
val fp_toint_cmd = Reg() { Bits() }
when (fpdec.io.toint) {
when (reg_valid) {
when (ctrl.toint) {
fp_toint_data := ex_rs1
}
when (fpdec.io.store) {
when (ctrl.store) {
fp_toint_data := ex_rs2
}
io.dpath.store_data := fp_toint_data
when (ctrl.toint || ctrl.store) {
fp_toint_single := ctrl.single
fp_toint_cmd := ctrl.cmd
}
}
// currently we assume FP stores and FP->int ops take 1 cycle (MEM)
val fpiu = new rocketFPIntUnit
fpiu.io.single := ctrl.single
fpiu.io.cmd := ctrl.cmd
fpiu.io.in := fp_toint_data
io.dpath.store_data := fpiu.io.out
val fsr_busy = ctrl.fsr && Bool(false)
val units_busy = Bool(false)
io.ctrl.nack := reg_valid && (fsr_busy || units_busy)
io.ctrl.dec <> fp_decoder.io.sigs
}