diff --git a/src/main/scala/TestBench.scala b/src/main/scala/TestBench.scala
index dc5c4f87..6e7842ab 100644
--- a/src/main/scala/TestBench.scala
+++ b/src/main/scala/TestBench.scala
@@ -17,18 +17,6 @@ object TestBenchGeneration extends FileSystemUtilities {
     // bit collection on the DirectC side.  I had to individually define the
     // wires.
 
-    val defs = s"""
-  reg htif_out_ready;
-  wire htif_in_valid;
-  wire [`HTIF_WIDTH-1:0] htif_in_bits;
-  wire htif_in_ready, htif_out_valid;
-  wire [`HTIF_WIDTH-1:0] htif_out_bits;
-
-  wire mem_bk_in_valid;
-  wire mem_bk_out_valid;
-  wire mem_bk_out_ready;
-  wire [`HTIF_WIDTH-1:0] mem_in_bits;
-"""
     val nasti_defs = (0 until nMemChannel) map { i => s"""
   wire ar_valid_$i;
   reg ar_ready_$i;
@@ -314,7 +302,7 @@ object TestBenchGeneration extends FileSystemUtilities {
 """ } mkString
 
     val f = createOutputFile(s"$topModuleName.$configClassName.tb.vfrag")
-    f.write(defs + nasti_defs + delays + nasti_delays + instantiation + ticks)
+    f.write(nasti_defs + delays + nasti_delays + instantiation + ticks)
     f.close
   }
 
diff --git a/vsrc/rocketTestHarness.v b/vsrc/rocketTestHarness.v
index 482df725..e244803a 100644
--- a/vsrc/rocketTestHarness.v
+++ b/vsrc/rocketTestHarness.v
@@ -79,6 +79,12 @@ module rocketTestHarness;
   wire         printf_cond = verbose && !reset;
   integer      stderr = 32'h80000002;
 
+  reg htif_out_ready;
+  reg htif_in_valid;
+  reg [`HTIF_WIDTH-1:0] htif_in_bits;
+  wire htif_in_ready, htif_out_valid;
+  wire [`HTIF_WIDTH-1:0] htif_out_bits;
+
 `include `TBVFRAG
 
   always @(posedge clk)
@@ -86,18 +92,13 @@ module rocketTestHarness;
     r_reset <= reset;
   end
 
-  reg htif_in_valid_premux;
-  reg [`HTIF_WIDTH-1:0] htif_in_bits_premux;
-  assign htif_in_bits = htif_in_bits_premux;
-  assign htif_in_valid = htif_in_valid_premux;
-  wire htif_in_ready_premux = htif_in_ready;
   reg [31:0] exit = 0;
 
   always @(posedge htif_clk)
   begin
     if (reset || r_reset)
     begin
-      htif_in_valid_premux <= 0;
+      htif_in_valid <= 0;
       htif_out_ready <= 0;
       exit <= 0;
     end
@@ -105,9 +106,9 @@ module rocketTestHarness;
     begin
       htif_tick
       (
-        htif_in_valid_premux,
-        htif_in_ready_premux,
-        htif_in_bits_premux,
+        htif_in_valid,
+        htif_in_ready,
+        htif_in_bits,
         htif_out_valid,
         htif_out_ready,
         htif_out_bits,
@@ -123,11 +124,6 @@ module rocketTestHarness;
   initial
   begin
     $value$plusargs("max-cycles=%d", max_cycles);
-`ifdef MEM_BACKUP_EN
-    $value$plusargs("loadmem=%s", loadmem);
-    if (loadmem)
-      $readmemh(loadmem, mem.ram);
-`endif
     verbose = $test$plusargs("verbose");
 `ifdef DEBUG
     if ($value$plusargs("vcdplusfile=%s", vcdplusfile))