riscv/rocket-chip
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fix w_last wire

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Howard Mao
2016-03-25 14:19:13 -07:00
parent 2b61f28356
commit 9b9c662952
1 changed files with 1 additions and 1 deletions
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src/main/scala/TestBench.scala
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@@ -48,7 +48,7 @@ object TestBenchGeneration extends FileSystemUtilities {
reg w_ready_$i;
wire [`MEM_STRB_BITS-1:0] w_strb_$i;
wire [`MEM_DATA_BITS-1:0] w_data_$i;
wire w_last;
wire w_last_$i;
reg r_valid_$i;
wire r_ready_$i;