riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

fix w_last wire

Browse Source
This commit is contained in:
Howard Mao committed 2016-03-29 20:16:07 -07:00
1 parent 2b61f28356
commit 9b9c662952
1 file changed
+1 -1
Download Patch File Download Diff File Expand all files Collapse all files
src/main/scala/TestBench.scala
+1 -1
View File
@@ -48,7 +48,7 @@ object TestBenchGeneration extends FileSystemUtilities {
reg w_ready_$i; reg w_ready_$i;
wire [`MEM_STRB_BITS-1:0] w_strb_$i; wire [`MEM_STRB_BITS-1:0] w_strb_$i;
wire [`MEM_DATA_BITS-1:0] w_data_$i; wire [`MEM_DATA_BITS-1:0] w_data_$i;
wire w_last; wire w_last_$i;
reg r_valid_$i; reg r_valid_$i;
wire r_ready_$i; wire r_ready_$i;