riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Only look at error signal on last beat

Browse Source
This commit is contained in:
Andrew Waterman 2017-09-20 15:15:21 -07:00
parent 1cb91eed41
commit 9b828a2640
1 changed files with 1 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/rocket/ICache.scala
View File

@ -177,15 +177,13 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
val icache_tag_array = SeqMem(nSets, Vec(nWays, UInt(width = tECC.width(1 + tagBits))))
val tag_rdata = icache_tag_array.read(s0_vaddr(untagBits-1,blockOffBits), !refill_done && s0_valid)
val accruedRefillError = Reg(Bool())
val refillError = tl_out.d.bits.error || (refill_cnt > 0 && accruedRefillError)
when (refill_done) {
val enc_tag = tECC.encode(Cat(refillError, refill_tag))
val enc_tag = tECC.encode(Cat(tl_out.d.bits.error, refill_tag))
icache_tag_array.write(refill_idx, Vec.fill(nWays)(enc_tag), Seq.tabulate(nWays)(repl_way === _))
}
val vb_array = Reg(init=Bits(0, nSets*nWays))
when (refill_one_beat) {
accruedRefillError := refillError
// clear bit when refill starts so hit-under-miss doesn't fetch bad data
vb_array := vb_array.bitSet(Cat(repl_way, refill_idx), refill_done && !invalidated)
}