riscv/rocket-chip
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clint: support a configurable number of interrupt register stages

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This commit is contained in:
Wesley W. Terpstra 2017-09-06 14:20:46 -07:00
parent 929a924779
commit 9b55063de6
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/devices/tilelink/Clint.scala
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@ -25,7 +25,7 @@ object ClintConsts
def ints = 2
}
case class ClintParams(baseAddress: BigInt = 0x02000000)
case class ClintParams(baseAddress: BigInt = 0x02000000, intStages: Int = 0)
{
def address = AddressSet(baseAddress, ClintConsts.size-1)
}
@ -71,8 +71,8 @@ class CoreplexLocalInterrupter(params: ClintParams)(implicit p: Parameters) exte
val ipi = Seq.fill(nTiles) { RegInit(UInt(0, width = 1)) }
io.int.zipWithIndex.foreach { case (int, i) =>
int(0) := ipi(i)(0) // msip
int(1) := time.asUInt >= timecmp(i).asUInt // mtip
int(0) := ShiftRegister(ipi(i)(0), params.intStages) // msip
int(1) := ShiftRegister(time.asUInt >= timecmp(i).asUInt, params.intStages) // mtip
}
/* 0000 msip hart 0