riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Update README.md

Browse Source 
typo?
This commit is contained in:
RainerWasserfuhr 2014-10-08 01:46:48 +02:00
parent f15baeea49
commit 9b41ad92ba
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -323,7 +323,7 @@ We use Synopsys VCS for Verilog simulation. We acknowledge that using a
proprietary Verilog simulation tool for an open-source project is not proprietary Verilog simulation tool for an open-source project is not
ideal; we ask the community to help us move DirectC routines (VCS's way ideal; we ask the community to help us move DirectC routines (VCS's way
of gluing Verilog testbenches to arbitrary C/C++ code) into DPI/VPI of gluing Verilog testbenches to arbitrary C/C++ code) into DPI/VPI
routines so that we can make Verilog simulation work with a open-source routines so that we can make Verilog simulation work with an open-source
Verilog simulator. In the meantime, you can use the C++ emulator to Verilog simulator. In the meantime, you can use the C++ emulator to
generate vcd waveforms, which you can view with an open-source waveform generate vcd waveforms, which you can view with an open-source waveform
viewer such as GTKWave. viewer such as GTKWave.