From 75512e9aa09ee8696bf31806f8109d43d4ec2f8d Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Thu, 1 Dec 2016 14:55:25 -0800 Subject: [PATCH 1/5] minor Changes needed to support formal tests --- src/main/scala/diplomacy/LazyModule.scala | 3 +++ src/main/scala/uncore/tilelink2/Edges.scala | 18 ++++++++++++++++++ .../scala/uncore/tilelink2/Fragmenter.scala | 2 +- src/main/scala/uncore/tilelink2/Monitor.scala | 4 ++++ .../scala/uncore/tilelink2/Parameters.scala | 4 ++-- 5 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/main/scala/diplomacy/LazyModule.scala b/src/main/scala/diplomacy/LazyModule.scala index 5de4877c..79bf3b6d 100644 --- a/src/main/scala/diplomacy/LazyModule.scala +++ b/src/main/scala/diplomacy/LazyModule.scala @@ -91,7 +91,10 @@ object LazyModule protected[diplomacy] var stack = List[LazyModule]() private var index = 0 + var module_list = List[LazyModule]() + def apply[T <: LazyModule](bc: T)(implicit sourceInfo: SourceInfo): T = { + module_list = bc :: module_list // Make sure the user put LazyModule around modules in the correct order // If this require fails, probably some grandchild was missing a LazyModule // ... or you applied LazyModule twice diff --git a/src/main/scala/uncore/tilelink2/Edges.scala b/src/main/scala/uncore/tilelink2/Edges.scala index a7cb2df6..4df9a1b5 100644 --- a/src/main/scala/uncore/tilelink2/Edges.scala +++ b/src/main/scala/uncore/tilelink2/Edges.scala @@ -95,6 +95,24 @@ class TLEdge( staticHasData(x).map(Bool(_)).getOrElse(opdata) } + def opcode(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.opcode + case b: TLBundleB => b.opcode + case c: TLBundleC => c.opcode + case d: TLBundleD => d.opcode + } + } + + def param(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.param + case b: TLBundleB => b.param + case c: TLBundleC => c.param + case d: TLBundleD => d.param + } + } + def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index 3c5c319f..4e6592dc 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -13,7 +13,7 @@ import scala.math.{min,max} // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides -class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) extends LazyModule +class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false) extends LazyModule { require (isPow2 (maxSize)) require (isPow2 (minSize)) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index a8af77e3..b993c490 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -415,11 +415,15 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source legalizeSourceUnique(bundle, edge) } + var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {} + lazy val module = new LazyModuleImp(this) { val io = new Bundle { val in = gen().asInput } + code_insertion(io.in, edge()) + legalize(io.in, edge())(sourceInfo) } } diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index f732efd9..19dd9604 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - address: Seq[AddressSet], + val address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - executable: Boolean = false, // processor can execute from this memory + val executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none, From 5e9496fd14b0ca648aea69ac933023476c61bc27 Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Thu, 1 Dec 2016 14:55:25 -0800 Subject: [PATCH 2/5] minor Changes needed to support formal tests --- src/main/scala/diplomacy/LazyModule.scala | 3 +++ src/main/scala/uncore/tilelink2/Edges.scala | 18 ++++++++++++++++++ .../scala/uncore/tilelink2/Fragmenter.scala | 2 +- src/main/scala/uncore/tilelink2/Monitor.scala | 4 ++++ .../scala/uncore/tilelink2/Parameters.scala | 4 ++-- 5 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/main/scala/diplomacy/LazyModule.scala b/src/main/scala/diplomacy/LazyModule.scala index 3b7de281..52824f47 100644 --- a/src/main/scala/diplomacy/LazyModule.scala +++ b/src/main/scala/diplomacy/LazyModule.scala @@ -91,7 +91,10 @@ object LazyModule protected[diplomacy] var stack = List[LazyModule]() private var index = 0 + var module_list = List[LazyModule]() + def apply[T <: LazyModule](bc: T)(implicit sourceInfo: SourceInfo): T = { + module_list = bc :: module_list // Make sure the user put LazyModule around modules in the correct order // If this require fails, probably some grandchild was missing a LazyModule // ... or you applied LazyModule twice diff --git a/src/main/scala/uncore/tilelink2/Edges.scala b/src/main/scala/uncore/tilelink2/Edges.scala index 92deb987..e794d846 100644 --- a/src/main/scala/uncore/tilelink2/Edges.scala +++ b/src/main/scala/uncore/tilelink2/Edges.scala @@ -95,6 +95,24 @@ class TLEdge( staticHasData(x).map(Bool(_)).getOrElse(opdata) } + def opcode(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.opcode + case b: TLBundleB => b.opcode + case c: TLBundleC => c.opcode + case d: TLBundleD => d.opcode + } + } + + def param(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.param + case b: TLBundleB => b.param + case c: TLBundleC => c.param + case d: TLBundleD => d.param + } + } + def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index fd9a44d2..21817bb1 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -13,7 +13,7 @@ import scala.math.{min,max} // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides -class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) extends LazyModule +class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false) extends LazyModule { require (isPow2 (maxSize)) require (isPow2 (minSize)) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index 9af850fd..072ecb11 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -415,11 +415,15 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source legalizeSourceUnique(bundle, edge) } + var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {} + lazy val module = new LazyModuleImp(this) { val io = new Bundle { val in = gen().asInput } + code_insertion(io.in, edge()) + legalize(io.in, edge())(sourceInfo) } } diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 7418d575..b60dea6d 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - address: Seq[AddressSet], + val address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - executable: Boolean = false, // processor can execute from this memory + val executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none, From cff2612cdb2ac0eb9e353cd28b748795a3479007 Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Thu, 1 Dec 2016 14:55:25 -0800 Subject: [PATCH 3/5] minor Changes needed to support formal tests --- src/main/scala/diplomacy/LazyModule.scala | 3 +++ src/main/scala/uncore/tilelink2/Edges.scala | 18 ++++++++++++++++++ .../scala/uncore/tilelink2/Fragmenter.scala | 2 +- src/main/scala/uncore/tilelink2/Monitor.scala | 4 ++++ .../scala/uncore/tilelink2/Parameters.scala | 4 ++-- 5 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/main/scala/diplomacy/LazyModule.scala b/src/main/scala/diplomacy/LazyModule.scala index 3b7de281..52824f47 100644 --- a/src/main/scala/diplomacy/LazyModule.scala +++ b/src/main/scala/diplomacy/LazyModule.scala @@ -91,7 +91,10 @@ object LazyModule protected[diplomacy] var stack = List[LazyModule]() private var index = 0 + var module_list = List[LazyModule]() + def apply[T <: LazyModule](bc: T)(implicit sourceInfo: SourceInfo): T = { + module_list = bc :: module_list // Make sure the user put LazyModule around modules in the correct order // If this require fails, probably some grandchild was missing a LazyModule // ... or you applied LazyModule twice diff --git a/src/main/scala/uncore/tilelink2/Edges.scala b/src/main/scala/uncore/tilelink2/Edges.scala index 92deb987..e794d846 100644 --- a/src/main/scala/uncore/tilelink2/Edges.scala +++ b/src/main/scala/uncore/tilelink2/Edges.scala @@ -95,6 +95,24 @@ class TLEdge( staticHasData(x).map(Bool(_)).getOrElse(opdata) } + def opcode(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.opcode + case b: TLBundleB => b.opcode + case c: TLBundleC => c.opcode + case d: TLBundleD => d.opcode + } + } + + def param(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.param + case b: TLBundleB => b.param + case c: TLBundleC => c.param + case d: TLBundleD => d.param + } + } + def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index fd9a44d2..21817bb1 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -13,7 +13,7 @@ import scala.math.{min,max} // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides -class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) extends LazyModule +class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false) extends LazyModule { require (isPow2 (maxSize)) require (isPow2 (minSize)) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index 9af850fd..072ecb11 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -415,11 +415,15 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source legalizeSourceUnique(bundle, edge) } + var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {} + lazy val module = new LazyModuleImp(this) { val io = new Bundle { val in = gen().asInput } + code_insertion(io.in, edge()) + legalize(io.in, edge())(sourceInfo) } } diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 7418d575..b60dea6d 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - address: Seq[AddressSet], + val address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - executable: Boolean = false, // processor can execute from this memory + val executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none, From 6d402ff1afb4fcf940806162d41f55bab9ea7b23 Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Thu, 1 Dec 2016 14:55:25 -0800 Subject: [PATCH 4/5] minor Changes needed to support formal tests --- src/main/scala/diplomacy/LazyModule.scala | 3 +++ src/main/scala/uncore/tilelink2/Edges.scala | 18 ++++++++++++++++++ .../scala/uncore/tilelink2/Fragmenter.scala | 2 +- src/main/scala/uncore/tilelink2/Monitor.scala | 4 ++++ .../scala/uncore/tilelink2/Parameters.scala | 4 ++-- 5 files changed, 28 insertions(+), 3 deletions(-) diff --git a/src/main/scala/diplomacy/LazyModule.scala b/src/main/scala/diplomacy/LazyModule.scala index 3b7de281..52824f47 100644 --- a/src/main/scala/diplomacy/LazyModule.scala +++ b/src/main/scala/diplomacy/LazyModule.scala @@ -91,7 +91,10 @@ object LazyModule protected[diplomacy] var stack = List[LazyModule]() private var index = 0 + var module_list = List[LazyModule]() + def apply[T <: LazyModule](bc: T)(implicit sourceInfo: SourceInfo): T = { + module_list = bc :: module_list // Make sure the user put LazyModule around modules in the correct order // If this require fails, probably some grandchild was missing a LazyModule // ... or you applied LazyModule twice diff --git a/src/main/scala/uncore/tilelink2/Edges.scala b/src/main/scala/uncore/tilelink2/Edges.scala index 92deb987..e794d846 100644 --- a/src/main/scala/uncore/tilelink2/Edges.scala +++ b/src/main/scala/uncore/tilelink2/Edges.scala @@ -95,6 +95,24 @@ class TLEdge( staticHasData(x).map(Bool(_)).getOrElse(opdata) } + def opcode(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.opcode + case b: TLBundleB => b.opcode + case c: TLBundleC => c.opcode + case d: TLBundleD => d.opcode + } + } + + def param(x: TLDataChannel): UInt = { + x match { + case a: TLBundleA => a.param + case b: TLBundleB => b.param + case c: TLBundleC => c.param + case d: TLBundleD => d.param + } + } + def size(x: TLDataChannel): UInt = { x match { case a: TLBundleA => a.size diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index fd9a44d2..21817bb1 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -13,7 +13,7 @@ import scala.math.{min,max} // Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint // Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin) // Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides -class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) extends LazyModule +class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false) extends LazyModule { require (isPow2 (maxSize)) require (isPow2 (minSize)) diff --git a/src/main/scala/uncore/tilelink2/Monitor.scala b/src/main/scala/uncore/tilelink2/Monitor.scala index 9af850fd..072ecb11 100644 --- a/src/main/scala/uncore/tilelink2/Monitor.scala +++ b/src/main/scala/uncore/tilelink2/Monitor.scala @@ -415,11 +415,15 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source legalizeSourceUnique(bundle, edge) } + var code_insertion = (bundle_monitor: TLBundleSnoop, edge: TLEdge) => {} + lazy val module = new LazyModuleImp(this) { val io = new Bundle { val in = gen().asInput } + code_insertion(io.in, edge()) + legalize(io.in, edge())(sourceInfo) } } diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index 7418d575..b60dea6d 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - address: Seq[AddressSet], + val address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - executable: Boolean = false, // processor can execute from this memory + val executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none, From be23189f77a4c482066dedbbb0520a1b66953263 Mon Sep 17 00:00:00 2001 From: Jacob Chang Date: Thu, 1 Dec 2016 18:35:43 -0800 Subject: [PATCH 5/5] Removed val from case class for Parameters --- src/main/scala/uncore/tilelink2/Parameters.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/Parameters.scala b/src/main/scala/uncore/tilelink2/Parameters.scala index b60dea6d..7418d575 100644 --- a/src/main/scala/uncore/tilelink2/Parameters.scala +++ b/src/main/scala/uncore/tilelink2/Parameters.scala @@ -7,9 +7,9 @@ import diplomacy._ import scala.math.max case class TLManagerParameters( - val address: Seq[AddressSet], + address: Seq[AddressSet], regionType: RegionType.T = RegionType.GET_EFFECTS, - val executable: Boolean = false, // processor can execute from this memory + executable: Boolean = false, // processor can execute from this memory nodePath: Seq[BaseNode] = Seq(), // Supports both Acquire+Release+Finish of these sizes supportsAcquire: TransferSizes = TransferSizes.none,