diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala
index ac842d85..44c3581a 100644
--- a/rocket/src/main/scala/arbiter.scala
+++ b/rocket/src/main/scala/arbiter.scala
@@ -1,8 +1,6 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
 import uncore._
 
 class HellaCacheArbiter(n: Int)(implicit conf: RocketConfiguration) extends Component
diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index b6c7fb82..d1ce166e 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -56,12 +56,6 @@ trait InterruptConstants {
   val CAUSE_INTERRUPT = 32
 }
  
-abstract trait RocketDcacheConstants extends uncore.constants.CacheConstants with uncore.constants.AddressConstants {
-  require(OFFSET_BITS == log2Up(uncore.Constants.CACHE_DATA_SIZE_IN_BYTES))
-  require(OFFSET_BITS <= uncore.Constants.ACQUIRE_WRITE_MASK_BITS)
-  require(log2Up(OFFSET_BITS) <= uncore.Constants.ACQUIRE_SUBWORD_ADDR_BITS)
-}
-
 trait VectorOpConstants {
   val VEC_X = Bits("b??", 2).toUFix
   val VEC_FN_N = UFix(0, 2)
diff --git a/rocket/src/main/scala/core.scala b/rocket/src/main/scala/core.scala
index 39209a62..81df73c4 100644
--- a/rocket/src/main/scala/core.scala
+++ b/rocket/src/main/scala/core.scala
@@ -1,9 +1,8 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
 import hwacha._
+import uncore.constants.MemoryOpConstants._
 import Util._
 
 class RocketIO(implicit conf: RocketConfiguration) extends Bundle
diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 8273deed..682af625 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -1,10 +1,9 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
 import Instructions._
 import hwacha._
+import uncore.constants.MemoryOpConstants._
 import ALU._
 import Util._
 
diff --git a/rocket/src/main/scala/ctrl_vec.scala b/rocket/src/main/scala/ctrl_vec.scala
index 35974ec9..a3179993 100644
--- a/rocket/src/main/scala/ctrl_vec.scala
+++ b/rocket/src/main/scala/ctrl_vec.scala
@@ -1,8 +1,6 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
 import Instructions._
 import hwacha.Constants._
 
diff --git a/rocket/src/main/scala/decode.scala b/rocket/src/main/scala/decode.scala
index a63c5c3d..bfea1102 100644
--- a/rocket/src/main/scala/decode.scala
+++ b/rocket/src/main/scala/decode.scala
@@ -88,7 +88,7 @@ object Simplify
         for (p <- r; if p.prime)
           prime = p :: prime
     }
-    prime.sort(_<_)
+    prime.sortWith(_<_)
   }
   def getEssentialPrimeImplicants(prime: Seq[Term], minterms: Seq[Term]): (Seq[Term],Seq[Term],Seq[Term]) = {
     for (i <- 0 until prime.size) {
@@ -116,7 +116,7 @@ object Simplify
     val ca = getCost(a, bits)
     val cb = getCost(b, bits)
     def listLess(a: List[Term], b: List[Term]): Boolean = !b.isEmpty && (a.isEmpty || a.head < b.head || a.head == b.head && listLess(a.tail, b.tail))
-    ca < cb || ca == cb && listLess(a.sort(_<_), b.sort(_<_))
+    ca < cb || ca == cb && listLess(a.sortWith(_<_), b.sortWith(_<_))
   }
   def getCover(implicants: Seq[Term], minterms: Seq[Term], bits: Int) = {
     if (minterms.nonEmpty) {
@@ -179,7 +179,7 @@ object SimplifyDC
         for (p <- r; if p.prime)
           prime = p :: prime
     }
-    prime.sort(_<_)
+    prime.sortWith(_<_)
   }
 
   def verify(cover: Seq[Term], minterms: Seq[Term], maxterms: Seq[Term]) = {
diff --git a/rocket/src/main/scala/divider.scala b/rocket/src/main/scala/divider.scala
index f76d38ed..91ce2122 100644
--- a/rocket/src/main/scala/divider.scala
+++ b/rocket/src/main/scala/divider.scala
@@ -1,8 +1,6 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
 import ALU._
 import Util._
 
diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala
index 8c0d0036..3f6a2677 100644
--- a/rocket/src/main/scala/dpath.scala
+++ b/rocket/src/main/scala/dpath.scala
@@ -1,11 +1,10 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
 import Instructions._
 import Util._
 import hwacha._
+import uncore.constants.AddressConstants._
 
 class Datapath(implicit conf: RocketConfiguration) extends Component
 {
diff --git a/rocket/src/main/scala/dpath_alu.scala b/rocket/src/main/scala/dpath_alu.scala
index 5a29ab20..3c751fe0 100644
--- a/rocket/src/main/scala/dpath_alu.scala
+++ b/rocket/src/main/scala/dpath_alu.scala
@@ -2,7 +2,6 @@ package rocket
 
 import Chisel._
 import Node._
-import Constants._
 import Instructions._
 
 object ALU
diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala
index 25fd8438..a3d3572e 100644
--- a/rocket/src/main/scala/dpath_util.scala
+++ b/rocket/src/main/scala/dpath_util.scala
@@ -1,10 +1,10 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
-import scala.math._
 import Util._
+import Node._
+import uncore.constants.AddressConstants._
+import scala.math._
 
 class DpathBTBIO extends Bundle
 {
diff --git a/rocket/src/main/scala/dpath_vec.scala b/rocket/src/main/scala/dpath_vec.scala
index caceae02..9300b012 100644
--- a/rocket/src/main/scala/dpath_vec.scala
+++ b/rocket/src/main/scala/dpath_vec.scala
@@ -2,7 +2,6 @@ package rocket
 
 import Chisel._
 import Node._
-import Constants._
 import Instructions._
 import hwacha.Constants._
 
diff --git a/rocket/src/main/scala/ecc.scala b/rocket/src/main/scala/ecc.scala
index 179315d6..d122e3a6 100644
--- a/rocket/src/main/scala/ecc.scala
+++ b/rocket/src/main/scala/ecc.scala
@@ -1,7 +1,6 @@
 package rocket
 
 import Chisel._
-import Constants._
 import uncore._
 import Util._
 
diff --git a/rocket/src/main/scala/fpu.scala b/rocket/src/main/scala/fpu.scala
index 41fd4cb4..f1eee8cb 100644
--- a/rocket/src/main/scala/fpu.scala
+++ b/rocket/src/main/scala/fpu.scala
@@ -1,11 +1,10 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
 import Instructions._
 import Util._
 import FPConstants._
+import uncore.constants.MemoryOpConstants._
 
 object FPConstants
 {
diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala
index 8a999419..6a21ed21 100644
--- a/rocket/src/main/scala/htif.scala
+++ b/rocket/src/main/scala/htif.scala
@@ -2,7 +2,6 @@ package rocket
 
 import Chisel._
 import Node._
-import Constants._
 import uncore._
 import Util._
 
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index 31810b60..23f27c9b 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -1,8 +1,6 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
 import uncore._
 import Util._
 
diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala
index 33446f3c..4c10f6b2 100644
--- a/rocket/src/main/scala/instructions.scala
+++ b/rocket/src/main/scala/instructions.scala
@@ -2,7 +2,6 @@ package rocket
 
 import Chisel._
 import Node._
-import Constants._
 
 object Instructions
 {
diff --git a/rocket/src/main/scala/multiplier.scala b/rocket/src/main/scala/multiplier.scala
index 79905b4e..06d35d8a 100644
--- a/rocket/src/main/scala/multiplier.scala
+++ b/rocket/src/main/scala/multiplier.scala
@@ -1,8 +1,6 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
 import ALU._
 
 class MultiplierReq(implicit conf: RocketConfiguration) extends Bundle {
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 78dbb61e..f4c26ed8 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -1,8 +1,6 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
 import uncore._
 import Util._
 
@@ -12,6 +10,9 @@ case class DCacheConfig(sets: Int, ways: Int, co: CoherencePolicy,
                         narrowRead: Boolean = true,
                         reqtagbits: Int = -1, databits: Int = -1)
 {
+  require(OFFSET_BITS == log2Up(CACHE_DATA_SIZE_IN_BYTES))
+  require(OFFSET_BITS <= ACQUIRE_WRITE_MASK_BITS)
+  require(log2Up(OFFSET_BITS) <= ACQUIRE_SUBWORD_ADDR_BITS)
   require(isPow2(sets))
   require(isPow2(ways)) // TODO: relax this
   def lines = sets*ways
diff --git a/rocket/src/main/scala/package.scala b/rocket/src/main/scala/package.scala
index dfc32dd4..ca2926fc 100644
--- a/rocket/src/main/scala/package.scala
+++ b/rocket/src/main/scala/package.scala
@@ -1,18 +1,7 @@
-package rocket
-import rocket.constants._
-
-import Chisel._
-import scala.math._
-
-//TODO: When compiler bug SI-5604 is fixed in 2.10, change object Constants to 
-//      package object rocket and remove import Constants._'s from other files
-object Constants extends 
-  ScalarOpConstants with
-  uncore.constants.MemoryOpConstants with
-  InterruptConstants with 
-  RocketDcacheConstants with
-  VectorOpConstants with 
-  uncore.constants.MemoryInterfaceConstants
+package object rocket extends 
+  rocket.constants.ScalarOpConstants with
+  rocket.constants.InterruptConstants with 
+  rocket.constants.VectorOpConstants
 {
   val START_ADDR = 0x2000
 }
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index bfc898c4..bcf9ce1b 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -1,8 +1,8 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
+import uncore.constants.AddressConstants._
+import uncore.constants.MemoryOpConstants._
 import Util._
 
 class TLBPTWIO extends Bundle {
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index 60cdc764..10ba3184 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -1,8 +1,6 @@
 package rocket
 
 import Chisel._
-import Node._
-import Constants._
 import uncore._
 import Util._
 
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index 33c4377d..a4dc13f6 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -1,9 +1,8 @@
 package rocket
 
-import Chisel._;
-import Node._;
-import Constants._;
-import scala.math._;
+import Chisel._
+import uncore.constants.AddressConstants._
+import scala.math._
 
 class ioCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle {
     val clear        = Bool(INPUT);