Merge pull request #1192 from seldridge/auto-plusargs
Automatic PlusArg for emulator.cc
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commit
9a56221566
@ -15,12 +15,20 @@
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#include <unistd.h>
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#include <getopt.h>
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//TODO: GENERATE THESE AUTOMATICALLY!
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static const char * verilog_plusargs [] = { "max-core-cycles",
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"jtag_rbb_enable",
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"tilelink_timeout",
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0};
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// For option parsing, which is split across this file, Verilog, and
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// FESVR's HTIF, a few external files must be pulled in. The list of
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// files and what they provide is enumerated:
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//
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// $RISCV/include/fesvr/htif.h:
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// defines:
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// - HTIF_USAGE_OPTIONS
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// - HTIF_LONG_OPTIONS_OPTIND
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// - HTIF_LONG_OPTIONS
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// $(ROCKETCHIP_DIR)/generated-src(-debug)?/$(CONFIG).plusArgs:
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// defines:
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// - PLUSARG_USAGE_OPTIONS
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// variables:
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// - static const char * verilog_plusargs
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extern dtm_t* dtm;
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extern remote_bitbang_t * jtag;
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@ -66,7 +74,7 @@ EMULATOR OPTIONS\n\
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#if VM_TRACE == 0
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fputs("\
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\n\
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EMULATOR OPTIONS (only supported in debug build -- try `make debug`)\n",
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EMULATOR DEBUG OPTIONS (only supported in debug build -- try `make debug`)\n",
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stdout);
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#endif
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fputs("\
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@ -74,14 +82,7 @@ EMULATOR OPTIONS (only supported in debug build -- try `make debug`)\n",
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-x, --dump-start=CYCLE Start VCD tracing at CYCLE\n\
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+dump-start\n\
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", stdout);
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fputs("\
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\n\
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VERILOG PLUSARGS (accepted by the Verilog itself):\n" , stdout);
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const char ** vpa = &verilog_plusargs[0];
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while (*vpa) {
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fprintf(stdout, " +%s=...\n", *vpa);
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vpa ++;
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}
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fputs("\n" PLUSARG_USAGE_OPTIONS, stdout);
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fputs("\n" HTIF_USAGE_OPTIONS, stdout);
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printf("\n"
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"EXAMPLES\n"
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@ -95,7 +96,11 @@ VERILOG PLUSARGS (accepted by the Verilog itself):\n" , stdout);
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#endif
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" - run an ELF (you wrote, called 'hello') using the proxy kernel:\n"
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" %s pk hello\n",
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program_name, program_name, program_name, program_name);
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program_name, program_name, program_name
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#if VM_TRACE
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, program_name
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#endif
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);
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}
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int main(int argc, char** argv)
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@ -204,7 +209,8 @@ int main(int argc, char** argv)
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}
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htif_option++;
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}
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std::cerr << argv[0] << ": invalid HTIF legacy plus-arg \"" << arg << "\"\n";
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std::cerr << argv[0] << ": invalid plus-arg (Verilog or HTIF) \""
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<< arg << "\"\n";
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c = '?';
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}
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goto retry;
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@ -60,7 +60,7 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
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--output-split-cfuncs 20000 \
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-Wno-STMTDLY --x-assign unique \
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-I$(base_dir)/vsrc \
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-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -DTEST_HARNESS=V$(MODEL) -include $(base_dir)/csrc/verilator.h"
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-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -DTEST_HARNESS=V$(MODEL) -include $(base_dir)/csrc/verilator.h -include $(generated_dir)/$(PROJECT).$(CONFIG).plusArgs"
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cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
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headers = $(wildcard $(base_dir)/csrc/*.h)
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@ -21,6 +21,7 @@ abstract class BareCoreplexModule[+L <: BareCoreplex](_outer: L) extends LazyMod
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ElaborationArtefacts.add("graphml", outer.graphML)
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ElaborationArtefacts.add("dts", outer.dts)
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ElaborationArtefacts.add("json", outer.json)
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ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
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println(outer.dts)
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}
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@ -728,7 +728,7 @@ class Rocket(implicit p: Parameters) extends CoreModule()(p)
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val max_core_cycles = PlusArg("max-core-cycles",
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default = 0,
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docstring = "Maximum Core Clock cycles simulation may run before timeout. Ignored if 0 (Default).")
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docstring = "Kill the emulation after INT rdtime cycles. Off if 0.")
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when (max_core_cycles > UInt(0)) {
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assert (csr.io.time < max_core_cycles, "Maximum Core Cycles reached.")
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}
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@ -442,7 +442,8 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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inflight := (inflight | a_set) & ~d_clr
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val watchdog = RegInit(UInt(0, width = 32))
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val limit = PlusArg("tilelink_timeout")
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val limit = PlusArg("tilelink_timeout",
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docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
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assert (!inflight.orR || limit === UInt(0) || watchdog < limit, "TileLink timeout expired" + extra)
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watchdog := watchdog + UInt(1)
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@ -5,7 +5,7 @@ package freechips.rocketchip.unittest
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import Chisel._
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import chisel3.experimental.MultiIOModule
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import freechips.rocketchip.config._
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import freechips.rocketchip.util.SimpleTimer
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import freechips.rocketchip.util._
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trait UnitTestIO {
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val finished = Bool(OUTPUT)
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@ -22,6 +22,7 @@ trait UnitTestLegacyModule extends HasUnitTestIO {
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trait UnitTestModule extends MultiIOModule with HasUnitTestIO {
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val io = IO(new Bundle with UnitTestIO)
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ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
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}
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abstract class UnitTest(val timeout: Int = 4096) extends Module with UnitTestLegacyModule {
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@ -124,7 +124,7 @@ trait GeneratorApp extends App with HasGeneratorUtilities {
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/** Output files created as a side-effect of elaboration */
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def generateArtefacts {
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ElaborationArtefacts.files.foreach { case (extension, contents) =>
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writeOutputFile(td, s"${names.configs}.${extension}", contents ())
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writeOutputFile(td, s"$longName.$extension", contents ())
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}
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}
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@ -4,6 +4,8 @@ package freechips.rocketchip.util
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import Chisel._
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case class PlusArgInfo(default: Int, docstring: String)
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class plusarg_reader(val format: String, val default: Int, val docstring: String) extends BlackBox(Map(
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"FORMAT" -> chisel3.core.StringParam(format),
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"DEFAULT" -> chisel3.core.IntParam(default))) {
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@ -20,6 +22,42 @@ object PlusArg
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// Add a docstring to document the arg, which can be dumped in an elaboration
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// pass.
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def apply(name: String, default: Int = 0, docstring: String = ""): UInt =
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def apply(name: String, default: Int = 0, docstring: String = ""): UInt = {
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PlusArgArtefacts.append(name, default, docstring)
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Module(new plusarg_reader(name + "=%d", default, docstring)).io.out
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}
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}
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object PlusArgArtefacts {
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private var artefacts: Map[String, PlusArgInfo] = Map.empty
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/* Add a new PlusArg */
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def append(name: String, default: Int, docstring: String): Unit =
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artefacts = artefacts ++ Map(name -> PlusArgInfo(default, docstring))
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/* From plus args, generate help text */
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private def serializeHelp_cHeader(tab: String = ""): String = artefacts
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.map{ case(arg, PlusArgInfo(default, docstring)) =>
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s"""|$tab+$arg=INT\\n\\
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|$tab${" "*20}$docstring\\n\\
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|$tab${" "*22}(default=$default)""".stripMargin }.toSeq
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.mkString("\\n\\\n") ++ "\""
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/* From plus args, generate a char array of their names */
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private def serializeArray_cHeader(tab: String = ""): String = {
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val prettyTab = tab + " " * 44 // Length of 'static const ...'
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s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
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artefacts
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.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
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.mkString("")++
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s"${prettyTab}0};"
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}
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/* Generate C code to be included in emulator.cc that helps with
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* argument parsing based on available Verilog PlusArgs */
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def serialize_cHeader(): String =
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s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
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|${serializeHelp_cHeader(" "*7)}
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|${serializeArray_cHeader()}
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|""".stripMargin
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}
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