tilelink: CacheCork uses constructor helpers
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@ -68,35 +68,25 @@ class TLCacheCork(unsafe: Boolean = false)(implicit p: Parameters) extends LazyM
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// Upgrades are instantly successful
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a_d.valid := in.a.valid && toD
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a_d.bits.opcode := Grant
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a_d.bits.param := TLPermissions.toT
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a_d.bits.size := in.a.bits.size
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a_d.bits.source := in.a.bits.source
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a_d.bits.sink := UInt(0)
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a_d.bits.data := UInt(0)
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a_d.bits.error := Bool(false)
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a_d.bits := edgeIn.Grant(
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fromSink = UInt(0),
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toSource = in.a.bits.source,
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lgSize = in.a.bits.size,
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capPermissions = TLPermissions.toT)
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// Take ReleaseData from C to A; Release from C to D
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val c_a = Wire(out.a)
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c_a.valid := in.c.valid && in.c.bits.opcode === ReleaseData
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c_a.bits.opcode := PutFullData
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c_a.bits.param := UInt(0)
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c_a.bits.size := in.c.bits.size
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c_a.bits.source := in.c.bits.source << 1
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c_a.bits.address := in.c.bits.address
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c_a.bits.mask := edgeOut.mask(in.c.bits.address, in.c.bits.size)
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c_a.bits.data := in.c.bits.data
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c_a.bits := edgeOut.Put(
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fromSource = in.c.bits.source << 1,
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toAddress = in.c.bits.address,
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lgSize = in.c.bits.size,
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data = in.c.bits.data)._2
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// Releases without Data succeed instantly
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val c_d = Wire(in.d)
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c_d.valid := in.c.valid && in.c.bits.opcode === Release
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c_d.bits.opcode := ReleaseAck
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c_d.bits.param := UInt(0)
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c_d.bits.size := in.c.bits.size
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c_d.bits.source := in.c.bits.source
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c_d.bits.sink := UInt(0)
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c_d.bits.data := UInt(0)
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c_d.bits.error := Bool(false)
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c_d.bits := edgeIn.ReleaseAck(in.c.bits)
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assert (!in.c.valid || in.c.bits.opcode === Release || in.c.bits.opcode === ReleaseData)
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in.c.ready := Mux(in.c.bits.opcode === Release, c_d.ready, c_a.ready)
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