diff --git a/src/main/scala/coreplex/RISCVPlatform.scala b/src/main/scala/coreplex/RISCVPlatform.scala
index 4744ea85..e2e6d079 100644
--- a/src/main/scala/coreplex/RISCVPlatform.scala
+++ b/src/main/scala/coreplex/RISCVPlatform.scala
@@ -25,6 +25,7 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork {
   plic.intnode := intBar.intnode
 
   lazy val dts = DTS(bindingTree)
+  lazy val dtb = DTB(dts)
   lazy val json = JSON(bindingTree)
 }
 
diff --git a/src/main/scala/diplomacy/DeviceTree.scala b/src/main/scala/diplomacy/DeviceTree.scala
index 8a26991a..04c468f2 100644
--- a/src/main/scala/diplomacy/DeviceTree.scala
+++ b/src/main/scala/diplomacy/DeviceTree.scala
@@ -4,6 +4,8 @@ package diplomacy
 
 import Chisel._
 import config._
+import sys.process._
+import java.io.{ByteArrayInputStream, ByteArrayOutputStream}
 
 case object DTSModel    extends Field[String]
 case object DTSCompat   extends Field[Seq[String]] // -dev, -soc
@@ -115,3 +117,17 @@ object DTS
     case x: ResourceMap => fmtMap(x, indent, cells)
   }
 }
+
+case class DTB(contents: Seq[Byte])
+object DTB
+{
+  def apply(dts: String): DTB = {
+    val instream = new ByteArrayInputStream(dts.getBytes("UTF-8"))
+    val outstream = new ByteArrayOutputStream
+    val proc = "dtc -O dtb" #< instream #> outstream
+    require (proc.! == 0, "Failed to run dtc; is it in your path?")
+    instream.close
+    outstream.close
+    DTB(outstream.toByteArray)
+  }
+}
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index 65b59033..4d091e80 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -307,7 +307,7 @@ trait PeripheryBootROM {
 
   private val bootrom_address = 0x1000
   private val bootrom_size = 0x1000
-  private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.dts)
+  private lazy val bootrom_contents = GenerateBootROM(p, bootrom_address, coreplex.dtb)
   val bootrom = LazyModule(new TLROM(bootrom_address, bootrom_size, bootrom_contents, true, peripheryBusConfig.beatBytes))
   bootrom.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
 }
diff --git a/src/main/scala/rocketchip/Utils.scala b/src/main/scala/rocketchip/Utils.scala
index 31632741..c6910d69 100644
--- a/src/main/scala/rocketchip/Utils.scala
+++ b/src/main/scala/rocketchip/Utils.scala
@@ -53,17 +53,17 @@ class GlobalVariable[T] {
 }
 
 object GenerateBootROM {
-  def apply(p: Parameters, address: BigInt, dts: String) = {
+  def apply(p: Parameters, address: BigInt, dtb: DTB) = {
     val romdata = Files.readAllBytes(Paths.get(p(BootROMFile)))
     val rom = ByteBuffer.wrap(romdata)
 
     rom.order(ByteOrder.LITTLE_ENDIAN)
 
     require(address == address.toInt)
-    val dtsAddr = address.toInt + rom.capacity
+    val dtbAddr = address.toInt + rom.capacity
     require(rom.getInt(12) == 0,
       "DTS address position should not be occupied by code")
-    rom.putInt(12, dtsAddr)
-    rom.array() ++ (dts.getBytes.toSeq)
+    rom.putInt(12, dtbAddr)
+    rom.array() ++ dtb.contents
   }
 }