From 9a26cb7ec781edb2aa2319e0cdd1be72aad466ec Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 27 Oct 2016 18:38:14 -0700 Subject: [PATCH] Debug: mark the debug device executable --- src/main/scala/uncore/axi4/RegisterRouter.scala | 15 ++++++++------- src/main/scala/uncore/devices/Debug.scala | 2 +- .../scala/uncore/tilelink2/RegisterRouter.scala | 15 ++++++++------- 3 files changed, 17 insertions(+), 15 deletions(-) diff --git a/src/main/scala/uncore/axi4/RegisterRouter.scala b/src/main/scala/uncore/axi4/RegisterRouter.scala index 97b598d5..9f408c9a 100644 --- a/src/main/scala/uncore/axi4/RegisterRouter.scala +++ b/src/main/scala/uncore/axi4/RegisterRouter.scala @@ -7,10 +7,11 @@ import diplomacy._ import regmapper._ import scala.math.{min,max} -class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true) +class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) extends AXI4SlaveNode(AXI4SlavePortParameters( Seq(AXI4SlaveParameters( address = Seq(address), + executable = executable, supportsWrite = TransferSizes(1, beatBytes), supportsRead = TransferSizes(1, beatBytes), interleavedId = Some(0))), @@ -69,16 +70,16 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int object AXI4RegisterNode { - def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true) = - new AXI4RegisterNode(address, concurrency, beatBytes, undefZero) + def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) = + new AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable) } // These convenience methods below combine to make it possible to create a AXI4 // register mapped device from a totally abstract register mapped device. -abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean) extends LazyModule +abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean) extends LazyModule { - val node = AXI4RegisterNode(address, concurrency, beatBytes, undefZero) + val node = AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable) val intnode = uncore.tilelink2.IntSourceNode(interrupts) } @@ -101,10 +102,10 @@ class AXI4RegModule[P, B <: AXI4RegBundleBase](val params: P, bundleBuilder: => } class AXI4RegisterRouter[B <: AXI4RegBundleBase, M <: LazyModuleImp] - (val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true) + (val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) (bundleBuilder: AXI4RegBundleArg => B) (moduleBuilder: (=> B, AXI4RegisterRouterBase) => M) - extends AXI4RegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero) + extends AXI4RegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable) { require (isPow2(size)) // require (size >= 4096) ... not absolutely required, but highly recommended diff --git a/src/main/scala/uncore/devices/Debug.scala b/src/main/scala/uncore/devices/Debug.scala index e4ca2516..3ee83e9a 100644 --- a/src/main/scala/uncore/devices/Debug.scala +++ b/src/main/scala/uncore/devices/Debug.scala @@ -824,7 +824,7 @@ trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap { */ class TLDebugModule(address: BigInt = 0)(implicit p: Parameters) - extends TLRegisterRouter(address, beatBytes=p(rocket.XLen)/8)( + extends TLRegisterRouter(address, beatBytes=p(rocket.XLen)/8, executable=true)( new TLRegBundle(p, _ ) with DebugModuleBundle)( new TLRegModule(p, _, _) with DebugModule) diff --git a/src/main/scala/uncore/tilelink2/RegisterRouter.scala b/src/main/scala/uncore/tilelink2/RegisterRouter.scala index f8ab2fc3..d100917e 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouter.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouter.scala @@ -7,10 +7,11 @@ import diplomacy._ import regmapper._ import scala.math.{min,max} -class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true) +class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) extends TLManagerNode(TLManagerPortParameters( Seq(TLManagerParameters( address = Seq(address), + executable = executable, supportsGet = TransferSizes(1, beatBytes), supportsPutPartial = TransferSizes(1, beatBytes), supportsPutFull = TransferSizes(1, beatBytes), @@ -70,17 +71,17 @@ class TLRegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = object TLRegisterNode { - def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true) = - new TLRegisterNode(address, concurrency, beatBytes, undefZero) + def apply(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) = + new TLRegisterNode(address, concurrency, beatBytes, undefZero, executable) } // These convenience methods below combine to make it possible to create a TL2 // register mapped device from a totally abstract register mapped device. // See GPIO.scala in this directory for an example -abstract class TLRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean) extends LazyModule +abstract class TLRegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean) extends LazyModule { - val node = TLRegisterNode(address, concurrency, beatBytes, undefZero) + val node = TLRegisterNode(address, concurrency, beatBytes, undefZero, executable) val intnode = IntSourceNode(interrupts) } @@ -103,10 +104,10 @@ class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, r } class TLRegisterRouter[B <: TLRegBundleBase, M <: LazyModuleImp] - (val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true) + (val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false) (bundleBuilder: TLRegBundleArg => B) (moduleBuilder: (=> B, TLRegisterRouterBase) => M) - extends TLRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero) + extends TLRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable) { require (isPow2(size)) // require (size >= 4096) ... not absolutely required, but highly recommended