riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

andrew's fix for tlb lockup

Browse Source
This commit is contained in:
Yunsup Lee 2012-11-06 23:52:58 -08:00
parent 4d1ca8ba3a
commit 9a02298f6f
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/nbdcache.scala
View File

@ -807,7 +807,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
val dtlb = new TLB(8)
dtlb.io.ptw <> io.cpu.ptw
dtlb.io.req.valid := r_cpu_req_val_ && r_req_readwrite && !r_cpu_req_phys
dtlb.io.req.valid := r_cpu_req_val && r_req_readwrite && !r_cpu_req_phys
dtlb.io.req.bits.passthrough := r_cpu_req_phys
dtlb.io.req.bits.asid := UFix(0)
dtlb.io.req.bits.vpn := r_cpu_req_vpn