riscv/rocket-chip
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andrew's fix for tlb lockup

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Yunsup Lee committed 2012-11-06 23:52:58 -08:00
1 parent 4d1ca8ba3a
commit 9a02298f6f
1 file changed
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rocket/src/main/scala/nbdcache.scala
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@@ -807,7 +807,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
val dtlb = new TLB(8) val dtlb = new TLB(8)
dtlb.io.ptw <> io.cpu.ptw dtlb.io.ptw <> io.cpu.ptw
dtlb.io.req.valid := r_cpu_req_val_ && r_req_readwrite && !r_cpu_req_phys dtlb.io.req.valid := r_cpu_req_val && r_req_readwrite && !r_cpu_req_phys
dtlb.io.req.bits.passthrough := r_cpu_req_phys dtlb.io.req.bits.passthrough := r_cpu_req_phys
dtlb.io.req.bits.asid := UFix(0) dtlb.io.req.bits.asid := UFix(0)
dtlb.io.req.bits.vpn := r_cpu_req_vpn dtlb.io.req.bits.vpn := r_cpu_req_vpn