riscv/rocket-chip
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Swap order of ITIM WidthWidget and Fragmenter

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e99fa057ac accidentally reversed them
This commit is contained in:
Andrew Waterman 2017-04-27 15:30:02 -07:00
parent 8c10caeef9
commit 99de42d34c
1 changed files with 3 additions and 3 deletions
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src/main/scala/rocket/ScratchpadSlavePort.scala
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@ -113,9 +113,9 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend with HasCor
// 1) Frontend always exists, but may or may not have a scratchpad node // 1) Frontend always exists, but may or may not have a scratchpad node
val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), true)) val fg = LazyModule(new TLFragmenter(fetchWidth*coreInstBytes, p(CacheBlockBytes), true))
val ww = LazyModule(new TLWidthWidget(xLen/8)) val ww = LazyModule(new TLWidthWidget(xLen/8))
frontend.slaveNode :*= ww.node frontend.slaveNode :*= fg.node
ww.node :*= fg.node fg.node :*= ww.node
fg.node :*= slaveNode ww.node :*= slaveNode
// 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad // 2) ScratchpadSlavePort always has a node, but only exists when the HellaCache has a scratchpad
val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s => val scratch = tileParams.dcache.flatMap(d => d.scratch.map(s =>