tilelink2: allow preemption of Fragmenter and WidthWidget
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@ -191,7 +191,8 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else UInt(log2Ceil(m)))
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// Make the request Irrevocable
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val in_a = Queue(in.a, 1, flow=true)
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val repeat = Wire(Bool())
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val in_a = Repeater(in.a, repeat)
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// If this is infront of a single manager, these become constants
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val find = manager.findFast(edgeIn.address(in_a.bits))
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@ -226,10 +227,8 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
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when (out.a.fire()) { gennum := new_gennum }
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val delay = !aHasData && aFragnum =/= UInt(0)
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out.a.valid := in_a.valid
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in_a.ready := out.a.ready && !delay
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out.a.bits := in_a.bits
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repeat := !aHasData && aFragnum =/= UInt(0)
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out.a <> in_a
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out.a.bits.addr_hi := in_a.bits.addr_hi | (~aFragnum << log2Ceil(minSize/beatBytes) & aOrigOH1 >> log2Ceil(beatBytes))
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out.a.bits.source := Cat(in_a.bits.source, aFragnum)
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out.a.bits.size := aFrag
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37
src/main/scala/uncore/tilelink2/Repeater.scala
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37
src/main/scala/uncore/tilelink2/Repeater.scala
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@ -0,0 +1,37 @@
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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// A Repeater passes it's input to it's output, unless repeat is asserted.
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// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
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class Repeater[T <: Data](gen: T) extends Module
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{
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val io = new Bundle {
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val repeat = Bool(INPUT)
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val enq = Decoupled(gen).flip
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val deq = Decoupled(gen)
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}
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val full = RegInit(Bool(false))
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val saved = Reg(gen)
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// When !full, a repeater is pass-through
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io.deq.valid := io.enq.valid || full
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io.enq.ready := io.deq.ready && !full
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io.deq.bits := Mux(full, saved, io.enq.bits)
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when (io.enq.fire() && io.repeat) { full := Bool(true); saved := io.enq.bits }
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when (io.deq.fire() && !io.repeat) { full := Bool(false) }
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}
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object Repeater
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{
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def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
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val repeater = Module(new Repeater(enq.bits))
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repeater.io.repeat := repeat
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repeater.io.enq := enq
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repeater.io.deq
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}
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}
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@ -120,9 +120,7 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
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val dataOut = if (edgeIn.staticHasData(in.bits) == Some(false)) UInt(0) else Mux1H(select, dataSlices)
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val maskOut = Mux1H(select, maskSlices)
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in.ready := out.ready && last
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out.valid := in.valid
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out.bits := in.bits
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out <> in
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edgeOut.data(out.bits) := dataOut
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out.bits match {
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@ -133,6 +131,9 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
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}
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// addr_lo gets truncated automagically
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// Repeat the input if we're not last
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!last
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}
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def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
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@ -141,7 +142,8 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
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out <> in
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} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
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// split input to output
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split(edgeIn, Queue(in, 1, flow=true), edgeOut, out)
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val repeat = Wire(Bool())
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repeat := split(edgeIn, Repeater(in, repeat), edgeOut, out)
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} else {
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// merge input to output
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merge(edgeIn, in, edgeOut, out)
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