riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into HEAD

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Conflicts:
	src/main/scala/rocketchip/TestHarness.scala
This commit is contained in:
Megan Wachs
2016-08-23 07:34:01 -07:00
parent 96e2cefb34 61aa716f44
commit 9974626d6a
5 changed files with 92 additions and 79 deletions
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17
src/main/scala/rocketchip/TestHarness.scala
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@ -20,10 +20,8 @@ class TestHarness(implicit p: Parameters) extends Module {
require(dut.io.mem_tl.isEmpty)
require(dut.io.bus_clk.isEmpty)
require(dut.io.bus_rst.isEmpty)
require(dut.io.bus_axi.isEmpty)
require(dut.io.mmio_clk.isEmpty)
require(dut.io.mmio_rst.isEmpty)
require(dut.io.mmio_axi.isEmpty)
require(dut.io.mmio_ahb.isEmpty)
require(dut.io.mmio_tl.isEmpty)
require(dut.io.extra.elements.isEmpty)
@ -79,6 +77,21 @@ class TestHarness(implicit p: Parameters) extends Module {
stop(1)
}
}
for (bus_axi <- dut.io.bus_axi) {
bus_axi.ar.valid := Bool(false)
bus_axi.aw.valid := Bool(false)
bus_axi.w.valid := Bool(false)
bus_axi.r.ready := Bool(false)
bus_axi.b.ready := Bool(false)
}
for (mmio_axi <- dut.io.mmio_axi) {
val slave = Module(new NastiErrorSlave)
slave.io <> mmio_axi
}
}
}
class SimAXIMem(size: BigInt)(implicit p: Parameters) extends Module {