riscv/rocket-chip
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First stab at debug interrupts

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Andrew Waterman
2016-06-01 16:57:10 -07:00
parent 51379621d6
commit 9949347569
6 changed files with 108 additions and 18 deletions
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rocket/src/main/scala/util.scala
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@ -10,6 +10,7 @@ import cde.{Parameters, Field}
object Util {
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def intToUInt(x: Int): UInt = UInt(x)
implicit def bigIntToUInt(x: BigInt): UInt = UInt(x)
implicit def booleanToBool(x: Boolean): Bits = Bool(x)
implicit def intSeqToUIntSeq(x: Seq[Int]): Seq[UInt] = x.map(UInt(_))
implicit def seqToVec[T <: Data](x: Seq[T]): Vec[T] = Vec(x)