riscv/rocket-chip
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First stab at debug interrupts

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This commit is contained in:
Andrew Waterman
2016-06-01 16:57:10 -07:00
parent 51379621d6
commit 9949347569
6 changed files with 108 additions and 18 deletions
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rocket/src/main/scala/tlb.scala
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@ -128,7 +128,7 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
val do_mprv = io.ptw.status.mprv && !io.req.bits.instruction
val priv = Mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv)
val priv_s = priv === PRV.S
val priv_uses_vm = priv <= PRV.S
val priv_uses_vm = priv <= PRV.S && !io.ptw.status.debug
val req_xwr = Cat(!r_req.store, r_req.store, !(r_req.instruction || r_req.store))
val ur_bits = ur_array.toBits