riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Correction to probe reply w/ data handling

Browse Source
This commit is contained in:
Henry Cook 2012-03-02 13:41:01 -08:00
parent 6ad7aa5cdc
commit 993341d27e
1 changed files with 16 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
uncore/coherence.scala
View File

@ -31,8 +31,7 @@ class HubMemReq extends Bundle {
} }
class TrackerProbeData extends Bundle { class TrackerProbeData extends Bundle {
val valid = Bool() val tile_id = Bits(width = TILE_ID_BITS)
val data_tile_id = Bits(width = log2up(NTILES))
} }
class TrackerAllocReq extends Bundle { class TrackerAllocReq extends Bundle {
@ -182,7 +181,7 @@ trait FourStateCoherence extends CoherencePolicy {
class XactTracker(id: Int) extends Component with CoherencePolicy { class XactTracker(id: Int) extends Component with CoherencePolicy {
val io = new Bundle { val io = new Bundle {
val alloc_req = (new ioDecoupled) { new TrackerAllocReq() }.flip val alloc_req = (new ioDecoupled) { new TrackerAllocReq() }.flip
val probe_data = (new TrackerProbeData).asInput val p_data = (new ioPipe) { new TrackerProbeData() }
val can_alloc = Bool(INPUT) val can_alloc = Bool(INPUT)
val xact_finish = Bool(INPUT) val xact_finish = Bool(INPUT)
val p_rep_cnt_dec = Bits(NTILES, INPUT) val p_rep_cnt_dec = Bits(NTILES, INPUT)
@ -331,9 +330,9 @@ class XactTracker(id: Int) extends Component with CoherencePolicy {
state := s_mem state := s_mem
} }
} }
when(io.probe_data.valid) { when(io.p_data.valid) {
p_rep_data_needs_write := Bool(true) p_rep_data_needs_write := Bool(true)
p_rep_tile_id_ := io.p_rep_tile_id p_rep_tile_id_ := io.p_data.bits.tile_id
} }
} }
is(s_mem) { is(s_mem) {
@ -413,7 +412,9 @@ class CoherenceHubBroadcast extends CoherenceHub {
val do_free_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} } val do_free_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
val p_rep_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(NTILES){ Wire(){Bool()} } } val p_rep_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(NTILES){ Wire(){Bool()} } }
val p_req_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(NTILES){ Wire(){Bool()} } } val p_req_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(NTILES){ Wire(){Bool()} } }
val sent_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} } val sent_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bool()} }
val p_data_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bits(width = TILE_ID_BITS)} }
val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Wire(){ Bool()} }
for( i <- 0 until NGLOBAL_XACTS) { for( i <- 0 until NGLOBAL_XACTS) {
val t = trackerList(i).io val t = trackerList(i).io
@ -425,11 +426,15 @@ class CoherenceHubBroadcast extends CoherenceHub {
sh_count_arr(i) := t.sharer_count sh_count_arr(i) := t.sharer_count
send_x_rep_ack_arr(i) := t.send_x_rep_ack send_x_rep_ack_arr(i) := t.send_x_rep_ack
t.xact_finish := do_free_arr(i) t.xact_finish := do_free_arr(i)
t.p_data.bits.tile_id := p_data_tile_id_arr(i)
t.p_data.valid := p_data_valid_arr(i)
t.p_rep_cnt_dec := p_rep_cnt_dec_arr(i).toBits t.p_rep_cnt_dec := p_rep_cnt_dec_arr(i).toBits
t.p_req_cnt_inc := p_req_cnt_inc_arr(i).toBits t.p_req_cnt_inc := p_req_cnt_inc_arr(i).toBits
t.sent_x_rep_ack := sent_x_rep_ack_arr(i) t.sent_x_rep_ack := sent_x_rep_ack_arr(i)
do_free_arr(i) := Bool(false) do_free_arr(i) := Bool(false)
sent_x_rep_ack_arr(i) := Bool(false) sent_x_rep_ack_arr(i) := Bool(false)
p_data_tile_id_arr(i) := Bits(0, width = TILE_ID_BITS)
p_data_valid_arr(i) := Bool(false)
for( j <- 0 until NTILES) { for( j <- 0 until NTILES) {
p_rep_cnt_dec_arr(i)(j) := Bool(false) p_rep_cnt_dec_arr(i)(j) := Bool(false)
p_req_cnt_inc_arr(i)(j) := Bool(false) p_req_cnt_inc_arr(i)(j) := Bool(false)
@ -491,6 +496,8 @@ class CoherenceHubBroadcast extends CoherenceHub {
val idx = p_rep.bits.global_xact_id val idx = p_rep.bits.global_xact_id
p_rep.ready := foldR(trackerList.map(_.io.pop_p_rep(j)))(_ || _) p_rep.ready := foldR(trackerList.map(_.io.pop_p_rep(j)))(_ || _)
p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data(j)))(_ || _) p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data(j)))(_ || _)
p_data_valid_arr(idx) := p_rep.valid && p_rep.bits.has_data
p_data_tile_id_arr(idx) := UFix(j)
} }
for( i <- 0 until NGLOBAL_XACTS ) { for( i <- 0 until NGLOBAL_XACTS ) {
trackerList(i).io.p_rep_data.valid := io.tiles(trackerList(i).io.p_rep_tile_id).probe_rep_data.valid trackerList(i).io.p_rep_data.valid := io.tiles(trackerList(i).io.p_rep_tile_id).probe_rep_data.valid