From 665c2a349c921e5af239edd8861625faa02f4894 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 27 Jun 2017 13:31:29 -0700 Subject: [PATCH 1/8] Correct Debug + WFI Interactions 1) Debug interrupt should end WFI 2) WFI should end immedately during single-step 3) WFI should act like NOP during Debug Mode --- src/main/scala/rocket/CSR.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index a51fbdfc..9b077f66 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -505,8 +505,8 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param val exception = insn_call || insn_break || io.exception assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") - when (insn_wfi) { reg_wfi := true } - when (pending_interrupts.orR || exception) { reg_wfi := false } + when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true } + when (pending_interrupts.orR || exception || reg_dcsr.debugint) { reg_wfi := false } assert(!reg_wfi || io.retire === UInt(0)) when (io.retire(0) || exception) { reg_singleStepped := true } From 56839b2c625441db94268aaf1f6cf0989ca2fc9b Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 27 Jun 2017 13:34:55 -0700 Subject: [PATCH 2/8] debug: Remove DebugInterrupt from DCSR (it is no longer part of V13 spec) --- src/main/scala/rocket/CSR.scala | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 9b077f66..377eb427 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -59,9 +59,7 @@ class DCSR extends Bundle { val stopcycle = Bool() val stoptime = Bool() val cause = UInt(width = 3) - // TODO: debugint is not in the Debug Spec v13 - val debugint = Bool() - val zero1 = UInt(width=2) + val zero1 = UInt(width=3) val step = Bool() val prv = UInt(width = PRV.SZ) } @@ -312,7 +310,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param io.pmp := reg_pmp.map(PMP(_)) // debug interrupts are only masked by being in debug mode - when (Bool(usingDebug) && reg_dcsr.debugint && !reg_debug) { + when (Bool(usingDebug) && reg_debugint && !reg_debug) { io.interrupt := true io.interrupt_cause := UInt(interruptMSB) + CSR.debugIntCause } @@ -506,7 +504,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1, "these conditions must be mutually exclusive") when (insn_wfi && !io.singleStep && !reg_debug) { reg_wfi := true } - when (pending_interrupts.orR || exception || reg_dcsr.debugint) { reg_wfi := false } + when (pending_interrupts.orR || exception || reg_debugint) { reg_wfi := false } assert(!reg_wfi || io.retire === UInt(0)) when (io.retire(0) || exception) { reg_singleStepped := true } @@ -721,7 +719,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param reg_mip.mtip := io.interrupts.mtip reg_mip.msip := io.interrupts.msip reg_mip.meip := io.interrupts.meip - reg_dcsr.debugint := io.interrupts.debug + reg_debugint := RegInit(Bool(false), next = io.interrupts.debug) if (!usingVM) { reg_mideleg := 0 From 3b9550ede38d833842086976f9b4c8e0872f3c84 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 27 Jun 2017 13:38:02 -0700 Subject: [PATCH 3/8] debug: correctly declare reg_debugint --- src/main/scala/rocket/CSR.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 377eb427..e90e92ca 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -212,6 +212,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param reset_dcsr.xdebugver := 1 reset_dcsr.prv := PRV.M val reg_dcsr = Reg(init=reset_dcsr) + val reg_debugint = RegInit(Bool(false), next = io.interrupts.debug) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) @@ -719,7 +720,6 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param reg_mip.mtip := io.interrupts.mtip reg_mip.msip := io.interrupts.msip reg_mip.meip := io.interrupts.meip - reg_debugint := RegInit(Bool(false), next = io.interrupts.debug) if (!usingVM) { reg_mideleg := 0 From 136e4b6c27e460e3c98c56191b5c5167cbe00114 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 27 Jun 2017 13:39:44 -0700 Subject: [PATCH 4/8] debug: use consistent coding style (Reg(init ... ) vs RegInit) --- src/main/scala/rocket/CSR.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index e90e92ca..323477e4 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -212,7 +212,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param reset_dcsr.xdebugver := 1 reset_dcsr.prv := PRV.M val reg_dcsr = Reg(init=reset_dcsr) - val reg_debugint = RegInit(Bool(false), next = io.interrupts.debug) + val reg_debugint = Reg(init=Bool(false), next=io.interrupts.debug) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) From e1fe0f245bdd13a5b90a3e77c681446dbd780298 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 27 Jun 2017 14:10:13 -0700 Subject: [PATCH 5/8] debug: Don't reset debugint register, as none of the interrupt registers are. --- src/main/scala/rocket/CSR.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala index 323477e4..ab2f3d73 100644 --- a/src/main/scala/rocket/CSR.scala +++ b/src/main/scala/rocket/CSR.scala @@ -212,7 +212,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param reset_dcsr.xdebugver := 1 reset_dcsr.prv := PRV.M val reg_dcsr = Reg(init=reset_dcsr) - val reg_debugint = Reg(init=Bool(false), next=io.interrupts.debug) + val reg_debugint = Reg(Bool()) val (supported_interrupts, delegable_interrupts) = { val sup = Wire(new MIP) @@ -720,6 +720,7 @@ class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Param reg_mip.mtip := io.interrupts.mtip reg_mip.msip := io.interrupts.msip reg_mip.meip := io.interrupts.meip + reg_debugint := io.interrupts.debug if (!usingVM) { reg_mideleg := 0 From 3fc75c27141c4fbcbede477de7e44a1095e884df Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Tue, 27 Jun 2017 17:40:58 -0700 Subject: [PATCH 6/8] debug: report UNSUPPORTED more consistently. Allow haltreq/resumereq to be R as well as W. --- src/main/scala/uncore/devices/debug/Debug.scala | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/main/scala/uncore/devices/debug/Debug.scala b/src/main/scala/uncore/devices/debug/Debug.scala index a0b8ce46..b2b7ab4f 100644 --- a/src/main/scala/uncore/devices/debug/Debug.scala +++ b/src/main/scala/uncore/devices/debug/Debug.scala @@ -329,6 +329,8 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod when (DMCONTROLWrEn) { DMCONTROLNxt.ndmreset := DMCONTROLWrData.ndmreset DMCONTROLNxt.hartsel := DMCONTROLWrData.hartsel + DMCONTROLNxt.haltreq := DMCONTROLWrData.haltreq + DMCONTROLNxt.resumereq := DMCONTROLWrData.resumereq } } @@ -937,6 +939,8 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p: val commandWrIsAccessRegister = (COMMANDWrData.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) val commandRegIsAccessRegister = (COMMANDReg.cmdtype === DebugAbstractCommandType.AccessRegister.id.U) + val commandWrIsUnsupported = COMMANDWrEn && !commandWrIsAccessRegister; + val commandRegIsUnsupported = Wire(init = true.B) val commandRegBadHaltResume = Wire(init = false.B) when (commandRegIsAccessRegister) { @@ -954,16 +958,20 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int)(implicit p: // ----------------------- when (ctrlStateReg === CtrlState(Waiting)){ - when (wrAccessRegisterCommand || regAccessRegisterCommand) { ctrlStateNxt := CtrlState(CheckGenerate) + }.elsewhen (commandWrIsUnsupported) { // These checks are really on the command type. + errorUnsupported := true.B + }.elsewhen (autoexec && commandRegIsUnsupported) { + errorUnsupported := true.B } }.elsewhen (ctrlStateReg === CtrlState(CheckGenerate)){ // We use this state to ensure that the COMMAND has been // registered by the time that we need to use it, to avoid // generating it directly from the COMMANDWrData. - + // This 'commandRegIsUnsupported' is really just checking the + // AccessRegisterCommand parameters (regno) when (commandRegIsUnsupported) { errorUnsupported := true.B ctrlStateNxt := CtrlState(Waiting) From 35b89d8023d40d23bbe0f781816b58f165225821 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Wed, 28 Jun 2017 13:36:53 -0700 Subject: [PATCH 7/8] bump riscv-tools for fesvr-don't-die --- riscv-tools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-tools b/riscv-tools index 7cd1d105..aa244912 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit 7cd1d1057d3bcd040b9e655fd35f57ccc97e075a +Subproject commit aa244912e5895dceea54fd67880cdc5331eb5a6a From 39b06a917fadb75bb3546ce6faaf293060bc5914 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Wed, 28 Jun 2017 16:38:02 -0700 Subject: [PATCH 8/8] bump riscv-tools for fesvr-dont-die --- riscv-tools | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/riscv-tools b/riscv-tools index aa244912..75371b4e 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit aa244912e5895dceea54fd67880cdc5331eb5a6a +Subproject commit 75371b4e19435833f80767da691b718c68551f13