Move a bunch more things into util package
A lot of utility code was just being imported willy-nilly from one package to another. This moves the common code into util to make things more sensible. The code moved were * The AsyncQueue and AsyncDecoupledCrossing from junctions. * All of the code in rocket's util.scala * The BlackBox asynchronous reset registers from uncore.tilelink2 * The implicit definitions from uncore.util
This commit is contained in:
Howard Mao
100
src/main/scala/util/AsyncQueue.scala
Normal file
100
src/main/scala/util/AsyncQueue.scala
Normal file
@ -0,0 +1,100 @@
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// See LICENSE for license details.
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package util
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import Chisel._
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object GrayCounter {
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def apply(bits: Int, increment: Bool = Bool(true)): UInt = {
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val incremented = Wire(UInt(width=bits))
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val binary = AsyncResetReg(incremented, 0)
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incremented := binary + increment.asUInt()
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incremented ^ (incremented >> UInt(1))
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}
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}
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object AsyncGrayCounter {
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def apply(in: UInt, sync: Int): UInt = {
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val syncv = List.fill(sync)(Module (new AsyncResetRegVec(w = in.getWidth, 0)))
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syncv.last.io.d := in
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syncv.last.io.en := Bool(true)
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(syncv.init zip syncv.tail).foreach { case (sink, source) =>
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sink.io.d := source.io.q
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sink.io.en := Bool(true)
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}
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syncv(0).io.d
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}
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}
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class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int, clockIn: Clock, resetIn: Bool)
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extends Module(_clock = clockIn, _reset = resetIn) {
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val bits = log2Ceil(depth)
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val io = new Bundle {
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// These come from the source domain
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val enq = Decoupled(gen).flip()
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// These cross to the sink clock domain
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val ridx = UInt(INPUT, width = bits+1)
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val widx = UInt(OUTPUT, width = bits+1)
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val mem = Vec(depth, gen).asOutput
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}
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val mem = Reg(Vec(depth, gen)) //This does NOT need to be asynchronously reset.
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val widx = GrayCounter(bits+1, io.enq.fire())
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val ridx = AsyncGrayCounter(io.ridx, sync)
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val ready = widx =/= (ridx ^ UInt(depth | depth >> 1))
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val index = if (depth == 1) UInt(0) else io.widx(bits-1, 0) ^ (io.widx(bits, bits) << (bits-1))
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when (io.enq.fire() && !reset) { mem(index) := io.enq.bits }
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val ready_reg = AsyncResetReg(ready, 0)
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io.enq.ready := ready_reg
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val widx_reg = AsyncResetReg(widx, 0)
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io.widx := widx_reg
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io.mem := mem
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}
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class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int, clockIn: Clock, resetIn: Bool)
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extends Module(_clock = clockIn, _reset = resetIn) {
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val bits = log2Ceil(depth)
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val io = new Bundle {
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// These come from the sink domain
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val deq = Decoupled(gen)
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// These cross to the source clock domain
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val ridx = UInt(OUTPUT, width = bits+1)
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val widx = UInt(INPUT, width = bits+1)
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val mem = Vec(depth, gen).asInput
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}
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val ridx = GrayCounter(bits+1, io.deq.fire())
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val widx = AsyncGrayCounter(io.widx, sync)
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val valid = ridx =/= widx
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// The mux is safe because timing analysis ensures ridx has reached the register
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// On an ASIC, changes to the unread location cannot affect the selected value
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// On an FPGA, only one input changes at a time => mem updates don't cause glitches
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// The register only latches when the selected valued is not being written
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val index = if (depth == 1) UInt(0) else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
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// This register does not NEED to be reset, as its contents will not
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// be considered unless the asynchronously reset deq valid register is set.
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io.deq.bits := RegEnable(io.mem(index), valid)
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io.deq.valid := AsyncResetReg(valid, 0)
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io.ridx := AsyncResetReg(ridx, 0)
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}
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class AsyncQueue[T <: Data](gen: T, depth: Int = 8, sync: Int = 3) extends Crossing[T] {
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require (sync >= 2)
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require (depth > 0 && isPow2(depth))
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val io = new CrossingIO(gen)
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val source = Module(new AsyncQueueSource(gen, depth, sync, io.enq_clock, io.enq_reset))
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val sink = Module(new AsyncQueueSink (gen, depth, sync, io.deq_clock, io.deq_reset))
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source.io.enq <> io.enq
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io.deq <> sink.io.deq
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sink.io.mem := source.io.mem
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sink.io.widx := source.io.widx
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source.io.ridx := sink.io.ridx
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}
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110
src/main/scala/util/BlackBoxRegs.scala
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110
src/main/scala/util/BlackBoxRegs.scala
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@ -0,0 +1,110 @@
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package util
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import Chisel._
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import cde.{Parameters}
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/** This black-boxes an Async Reset
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* (or Set)
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* Register.
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*
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* Because Chisel doesn't support
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* parameterized black boxes,
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* we unfortunately have to
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* instantiate a number of these.
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*
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* We also have to hard-code the set/
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* reset behavior.
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*
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* Do not confuse an asynchronous
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* reset signal with an asynchronously
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* reset reg. You should still
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* properly synchronize your reset
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* deassertion.
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*
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* @param d Data input
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* @param q Data Output
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* @param clk Clock Input
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* @param rst Reset Input
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* @param en Write Enable Input
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*
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*/
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abstract class AbstractBBReg extends BlackBox {
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val io = new Bundle {
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val d = Bool(INPUT)
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val q = Bool(OUTPUT)
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val en = Bool(INPUT)
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val clk = Clock(INPUT)
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val rst = Bool(INPUT)
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}
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}
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class AsyncResetReg extends AbstractBBReg
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class AsyncSetReg extends AbstractBBReg
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class SimpleRegIO(val w: Int) extends Bundle{
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val d = UInt(INPUT, width = w)
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val q = UInt(OUTPUT, width = w)
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val en = Bool(INPUT)
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}
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class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
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val io = new SimpleRegIO(w)
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val bb_d = Mux(io.en, io.d, io.q)
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val async_regs: List[AbstractBBReg] = List.tabulate(w)(
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i => Module (
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if (((init >> i) % 2) > 0)
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new AsyncSetReg
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else
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new AsyncResetReg)
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)
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io.q := async_regs.map(_.io.q).asUInt
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for ((reg, idx) <- async_regs.zipWithIndex) {
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reg.io.clk := clock
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reg.io.rst := reset
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reg.io.d := bb_d(idx)
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reg.io.en := io.en
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}
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}
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object AsyncResetReg {
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def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean): Bool = {
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val reg: AbstractBBReg =
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if (init) Module (new AsyncSetReg)
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else Module(new AsyncResetReg)
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reg.io.d := d
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reg.io.clk := clk
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reg.io.rst := rst
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reg.io.en := Bool(true)
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reg.io.q
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}
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def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false)
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def apply(updateData: UInt, resetData: BigInt, enable: Bool): UInt = {
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val w = updateData.getWidth max resetData.bitLength
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val reg = Module(new AsyncResetRegVec(w, resetData))
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reg.io.d := updateData
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reg.io.en := enable
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reg.io.q
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}
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def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable=Bool(true))
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def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
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def apply(updateData: UInt): UInt = apply(updateData, resetData=BigInt(0), enable=Bool(true))
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}
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@ -2,6 +2,7 @@ package util
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import Chisel._
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import cde.Parameters
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import scala.math.max
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// Produces 0-width value when counting to 1
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class ZCounter(val n: Int) {
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@ -34,3 +35,33 @@ object TwoWayCounter {
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cnt
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}
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}
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// a counter that clock gates most of its MSBs using the LSB carry-out
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case class WideCounter(width: Int, inc: UInt = UInt(1), reset: Boolean = true)
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{
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private val isWide = width > 2*inc.getWidth
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private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
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private val small = if (reset) Reg(init=UInt(0, smallWidth)) else Reg(UInt(width = smallWidth))
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private val nextSmall = small +& inc
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small := nextSmall
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private val large = if (isWide) {
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val r = if (reset) Reg(init=UInt(0, width - smallWidth)) else Reg(UInt(width = width - smallWidth))
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when (nextSmall(smallWidth)) { r := r +& UInt(1) }
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r
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} else null
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val value = if (isWide) Cat(large, small) else small
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lazy val carryOut = {
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val lo = (small ^ nextSmall) >> 1
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if (!isWide) lo else {
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val hi = Mux(nextSmall(smallWidth), large ^ (large +& UInt(1)), UInt(0)) >> 1
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Cat(hi, lo)
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}
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}
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def := (x: UInt) = {
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small := x
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if (isWide) large := x >> smallWidth
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}
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}
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134
src/main/scala/util/Crossing.scala
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134
src/main/scala/util/Crossing.scala
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@ -0,0 +1,134 @@
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package util
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import Chisel._
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import chisel3.util.{DecoupledIO, Decoupled, Irrevocable, IrrevocableIO, ReadyValidIO}
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class CrossingIO[T <: Data](gen: T) extends Bundle {
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// Enqueue clock domain
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val enq_clock = Clock(INPUT)
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val enq_reset = Bool(INPUT) // synchronously deasserted wrt. enq_clock
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val enq = Decoupled(gen).flip()
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// Dequeue clock domain
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val deq_clock = Clock(INPUT)
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val deq_reset = Bool(INPUT) // synchronously deasserted wrt. deq_clock
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val deq = Decoupled(gen)
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}
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abstract class Crossing[T <: Data] extends Module {
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val io: CrossingIO[T]
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}
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class AsyncScope extends Module { val io = new Bundle }
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object AsyncScope { def apply() = Module(new AsyncScope) }
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object AsyncDecoupledCrossing
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{
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// takes from_source from the 'from' clock domain and puts it into the 'to' clock domain
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def apply[T <: Data](from_clock: Clock, from_reset: Bool, from_source: ReadyValidIO[T], to_clock: Clock, to_reset: Bool, depth: Int = 8, sync: Int = 3): DecoupledIO[T] = {
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val crossing = Module(new AsyncQueue(from_source.bits, depth, sync)).io
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crossing.enq_clock := from_clock
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crossing.enq_reset := from_reset
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crossing.enq <> from_source
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crossing.deq_clock := to_clock
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crossing.deq_reset := to_reset
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crossing.deq
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}
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}
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object AsyncDecoupledTo
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{
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// takes source from your clock domain and puts it into the 'to' clock domain
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def apply[T <: Data](to_clock: Clock, to_reset: Bool, source: ReadyValidIO[T], depth: Int = 8, sync: Int = 3): DecoupledIO[T] = {
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val scope = AsyncScope()
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AsyncDecoupledCrossing(scope.clock, scope.reset, source, to_clock, to_reset, depth, sync)
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}
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}
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object AsyncDecoupledFrom
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{
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// takes from_source from the 'from' clock domain and puts it into your clock domain
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def apply[T <: Data](from_clock: Clock, from_reset: Bool, from_source: ReadyValidIO[T], depth: Int = 8, sync: Int = 3): DecoupledIO[T] = {
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val scope = AsyncScope()
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AsyncDecoupledCrossing(from_clock, from_reset, from_source, scope.clock, scope.reset, depth, sync)
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}
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}
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object PostQueueIrrevocablize
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{
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def apply[T <: Data](deq: DecoupledIO[T]): IrrevocableIO[T] = {
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val irr = Wire(new IrrevocableIO(deq.bits))
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irr.bits := deq.bits
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irr.valid := deq.valid
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deq.ready := irr.ready
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irr
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}
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}
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object AsyncIrrevocableCrossing {
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def apply[T <: Data](from_clock: Clock, from_reset: Bool, from_source: ReadyValidIO[T], to_clock: Clock, to_reset: Bool, depth: Int = 8, sync: Int = 3): IrrevocableIO[T] = {
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PostQueueIrrevocablize(AsyncDecoupledCrossing(from_clock, from_reset, from_source, to_clock, to_reset, depth, sync))
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}
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}
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object AsyncIrrevocableTo
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{
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// takes source from your clock domain and puts it into the 'to' clock domain
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def apply[T <: Data](to_clock: Clock, to_reset: Bool, source: ReadyValidIO[T], depth: Int = 8, sync: Int = 3): IrrevocableIO[T] = {
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PostQueueIrrevocablize(AsyncDecoupledTo(to_clock, to_reset, source, depth, sync))
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}
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}
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object AsyncIrrevocableFrom
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{
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// takes from_source from the 'from' clock domain and puts it into your clock domain
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def apply[T <: Data](from_clock: Clock, from_reset: Bool, from_source: ReadyValidIO[T], depth: Int = 8, sync: Int = 3): IrrevocableIO[T] = {
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PostQueueIrrevocablize(AsyncDecoupledFrom(from_clock, from_reset, from_source, depth, sync))
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}
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}
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/**
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* This helper object synchronizes a level-sensitive signal from one
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* clock domain to another.
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*/
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object LevelSyncCrossing {
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class SynchronizerBackend(sync: Int, _clock: Clock) extends Module(Some(_clock)) {
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val io = new Bundle {
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val in = Bool(INPUT)
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val out = Bool(OUTPUT)
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}
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io.out := ShiftRegister(io.in, sync)
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}
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class SynchronizerFrontend(_clock: Clock) extends Module(Some(_clock)) {
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val io = new Bundle {
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val in = Bool(INPUT)
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val out = Bool(OUTPUT)
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}
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io.out := RegNext(io.in)
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}
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def apply(from_clock: Clock, to_clock: Clock, in: Bool, sync: Int = 2): Bool = {
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val front = Module(new SynchronizerFrontend(from_clock))
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val back = Module(new SynchronizerBackend(sync, to_clock))
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front.io.in := in
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back.io.in := front.io.out
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back.io.out
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}
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}
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object LevelSyncTo {
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def apply(to_clock: Clock, in: Bool, sync: Int = 2): Bool = {
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val scope = AsyncScope()
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LevelSyncCrossing(scope.clock, to_clock, in, sync)
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}
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}
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object LevelSyncFrom {
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def apply(from_clock: Clock, in: Bool, sync: Int = 2): Bool = {
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val scope = AsyncScope()
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LevelSyncCrossing(from_clock, scope.clock, in, sync)
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}
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}
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@ -2,6 +2,7 @@ package util
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import Chisel._
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import cde.Parameters
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import scala.math._
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class ParameterizedBundle(implicit p: Parameters) extends Bundle {
|
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override def cloneType = {
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@ -26,3 +27,113 @@ class DecoupledHelper(val rvs: Seq[Bool]) {
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(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
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}
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}
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object MuxT {
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def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
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(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
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def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
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(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
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}
|
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|
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object Str
|
||||
{
|
||||
def apply(s: String): UInt = {
|
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var i = BigInt(0)
|
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require(s.forall(validChar _))
|
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for (c <- s)
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i = (i << 8) | c
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UInt(i, s.length*8)
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}
|
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def apply(x: Char): UInt = {
|
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require(validChar(x))
|
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UInt(x.toInt, 8)
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}
|
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def apply(x: UInt): UInt = apply(x, 10)
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def apply(x: UInt, radix: Int): UInt = {
|
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val rad = UInt(radix)
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||||
val w = x.getWidth
|
||||
require(w > 0)
|
||||
|
||||
var q = x
|
||||
var s = digit(q % rad)
|
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for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
|
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q = q / rad
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s = Cat(Mux(Bool(radix == 10) && q === UInt(0), Str(' '), digit(q % rad)), s)
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||||
}
|
||||
s
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||||
}
|
||||
def apply(x: SInt): UInt = apply(x, 10)
|
||||
def apply(x: SInt, radix: Int): UInt = {
|
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val neg = x < SInt(0)
|
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val abs = x.abs
|
||||
if (radix != 10) {
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Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
|
||||
} else {
|
||||
val rad = UInt(radix)
|
||||
val w = abs.getWidth
|
||||
require(w > 0)
|
||||
|
||||
var q = abs
|
||||
var s = digit(q % rad)
|
||||
var needSign = neg
|
||||
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
|
||||
q = q / rad
|
||||
val placeSpace = q === UInt(0)
|
||||
val space = Mux(needSign, Str('-'), Str(' '))
|
||||
needSign = needSign && !placeSpace
|
||||
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
|
||||
}
|
||||
Cat(Mux(needSign, Str('-'), Str(' ')), s)
|
||||
}
|
||||
}
|
||||
|
||||
private def digit(d: UInt): UInt = Mux(d < UInt(10), Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
|
||||
private def validChar(x: Char) = x == (x & 0xFF)
|
||||
}
|
||||
|
||||
object Split
|
||||
{
|
||||
// is there a better way to do do this?
|
||||
def apply(x: Bits, n0: Int) = {
|
||||
val w = checkWidth(x, n0)
|
||||
(x(w-1,n0), x(n0-1,0))
|
||||
}
|
||||
def apply(x: Bits, n1: Int, n0: Int) = {
|
||||
val w = checkWidth(x, n1, n0)
|
||||
(x(w-1,n1), x(n1-1,n0), x(n0-1,0))
|
||||
}
|
||||
def apply(x: Bits, n2: Int, n1: Int, n0: Int) = {
|
||||
val w = checkWidth(x, n2, n1, n0)
|
||||
(x(w-1,n2), x(n2-1,n1), x(n1-1,n0), x(n0-1,0))
|
||||
}
|
||||
|
||||
private def checkWidth(x: Bits, n: Int*) = {
|
||||
val w = x.getWidth
|
||||
def decreasing(x: Seq[Int]): Boolean =
|
||||
if (x.tail.isEmpty) true
|
||||
else x.head >= x.tail.head && decreasing(x.tail)
|
||||
require(decreasing(w :: n.toList))
|
||||
w
|
||||
}
|
||||
}
|
||||
|
||||
object Random
|
||||
{
|
||||
def apply(mod: Int, random: UInt): UInt = {
|
||||
if (isPow2(mod)) random(log2Up(mod)-1,0)
|
||||
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
|
||||
}
|
||||
def apply(mod: Int): UInt = apply(mod, randomizer)
|
||||
def oneHot(mod: Int, random: UInt): UInt = {
|
||||
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
|
||||
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
|
||||
}
|
||||
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
|
||||
|
||||
private def randomizer = LFSR16()
|
||||
private def round(x: Double): Int =
|
||||
if (x.toInt.toDouble == x) x.toInt else (x.toInt + 1) & -2
|
||||
private def partition(value: UInt, slices: Int) =
|
||||
Seq.tabulate(slices)(i => value < round((i << value.getWidth).toDouble / slices))
|
||||
}
|
||||
|
||||
48
src/main/scala/util/Package.scala
Normal file
48
src/main/scala/util/Package.scala
Normal file
@ -0,0 +1,48 @@
|
||||
import Chisel._
|
||||
|
||||
package object util {
|
||||
implicit class UIntIsOneOf(val x: UInt) extends AnyVal {
|
||||
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).reduce(_||_)
|
||||
|
||||
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
|
||||
}
|
||||
|
||||
implicit class SeqToAugmentedSeq[T <: Data](val x: Seq[T]) extends AnyVal {
|
||||
def apply(idx: UInt): T = {
|
||||
if (x.size == 1) {
|
||||
x.head
|
||||
} else {
|
||||
val half = 1 << (log2Ceil(x.size) - 1)
|
||||
val newIdx = idx & UInt(half - 1)
|
||||
Mux(idx >= UInt(half), x.drop(half)(newIdx), x.take(half)(newIdx))
|
||||
}
|
||||
}
|
||||
|
||||
def asUInt(): UInt = Cat(x.map(_.asUInt).reverse)
|
||||
}
|
||||
|
||||
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
|
||||
implicit def intToUInt(x: Int): UInt = UInt(x)
|
||||
implicit def bigIntToUInt(x: BigInt): UInt = UInt(x)
|
||||
implicit def booleanToBool(x: Boolean): Bits = Bool(x)
|
||||
implicit def intSeqToUIntSeq(x: Seq[Int]): Seq[UInt] = x.map(UInt(_))
|
||||
implicit def wcToUInt(c: WideCounter): UInt = c.value
|
||||
|
||||
implicit class UIntToAugmentedUInt(val x: UInt) extends AnyVal {
|
||||
def sextTo(n: Int): UInt =
|
||||
if (x.getWidth == n) x
|
||||
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
|
||||
|
||||
def extract(hi: Int, lo: Int): UInt = {
|
||||
if (hi == lo-1) UInt(0)
|
||||
else x(hi, lo)
|
||||
}
|
||||
}
|
||||
|
||||
implicit class BooleanToAugmentedBoolean(val x: Boolean) extends AnyVal {
|
||||
def toInt: Int = if (x) 1 else 0
|
||||
|
||||
// this one's snagged from scalaz
|
||||
def option[T](z: => T): Option[T] = if (x) Some(z) else None
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user