Move a bunch more things into util package

A lot of utility code was just being imported willy-nilly from one
package to another. This moves the common code into util to make things
more sensible. The code moved were

 * The AsyncQueue and AsyncDecoupledCrossing from junctions.
 * All of the code in rocket's util.scala
 * The BlackBox asynchronous reset registers from uncore.tilelink2
 * The implicit definitions from uncore.util

src/main/scala/rocket/breakpoint.scala

@@ -3,8 +3,7 @@
 package rocket
 
 import Chisel._
-import Util._
-import uncore.util._
+import util._
 import cde.Parameters
 
 class BPControl(implicit p: Parameters) extends CoreBundle()(p) {

src/main/scala/rocket/btb.scala

@@ -4,10 +4,8 @@ package rocket
 
 import Chisel._
 import cde.{Parameters, Field}
-import Util._
-import uncore.util._
+import util._
 import uncore.agents.PseudoLRU
-import util.ParameterizedBundle
 
 case object BtbKey extends Field[BtbParameters]
 

src/main/scala/rocket/csr.scala

@@ -3,12 +3,10 @@
 package rocket
 
 import Chisel._
-import Util._
-import uncore.util._
 import Instructions._
 import cde.{Parameters, Field}
 import uncore.devices._
-import uncore.util._
+import util._
 import junctions.AddrMap
 
 class MStatus extends Bundle {

src/main/scala/rocket/dcache.scala

@@ -7,10 +7,10 @@ import junctions._
 import uncore.tilelink._
 import uncore.agents._
 import uncore.coherence._
-import uncore.util._
 import uncore.constants._
+import uncore.util._
+import util._
 import cde.{Parameters, Field}
-import Util._
 
 class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
   val addr = Bits(width = untagBits)

src/main/scala/rocket/fpu.scala

@@ -4,10 +4,9 @@ package rocket
 
 import Chisel._
 import Instructions._
-import Util._
+import util._
 import FPConstants._
 import uncore.constants.MemoryOpConstants._
-import uncore.util._
 import cde.{Parameters, Field}
 
 case class FPUConfig(

src/main/scala/rocket/frontend.scala

@@ -2,7 +2,7 @@ package rocket
 
 import Chisel._
 import uncore.tilelink._
-import Util._
+import util._
 import cde.{Parameters, Field}
 
 class FrontendReq(implicit p: Parameters) extends CoreBundle()(p) {

src/main/scala/rocket/ibuf.scala

@@ -3,9 +3,8 @@
 package rocket
 
 import Chisel._
-import Util._
+import util._
 import cde.{Parameters, Field}
-import util.ParameterizedBundle
 
 class Instruction(implicit val p: Parameters) extends ParameterizedBundle with HasCoreParameters {
   val pf0 = Bool() // page fault on first half of instruction

src/main/scala/rocket/icache.scala

@@ -4,7 +4,7 @@ import Chisel._
 import uncore.agents._
 import uncore.tilelink._
 import uncore.util._
-import Util._
+import util._
 import cde.{Parameters, Field}
 
 trait HasL1CacheParameters extends HasCacheParameters with HasCoreParameters {

src/main/scala/rocket/idecode.scala

@@ -7,7 +7,7 @@ import Instructions._
 import uncore.constants.MemoryOpConstants._
 import ALU._
 import cde.Parameters
-import Util._
+import util._
 
 abstract trait DecodeConstants extends HasCoreParameters
 {

src/main/scala/rocket/multiplier.scala

@@ -4,7 +4,7 @@ package rocket
 
 import Chisel._
 import ALU._
-import Util._
+import util._
 
 class MultiplierReq(dataBits: Int, tagBits: Int) extends Bundle {
   val fn = Bits(width = SZ_ALU_FN)

src/main/scala/rocket/nbdcache.scala

@@ -6,11 +6,10 @@ import Chisel._
 import uncore.tilelink._
 import uncore.coherence._
 import uncore.agents._
-import uncore.util._
 import uncore.constants._
-import util.{ParameterizedBundle, DecoupledHelper}
+import uncore.util._
+import util._
 import cde.{Parameters, Field}
-import Util._
 
 case class DCacheConfig(
   nMSHRs: Int = 1,

src/main/scala/rocket/ptw.scala

@@ -5,8 +5,7 @@ package rocket
 import Chisel._
 import uncore.agents._
 import uncore.constants._
-import Util._
-import uncore.util._
+import util._
 import cde.{Parameters, Field}
 
 class PTWReq(implicit p: Parameters) extends CoreBundle()(p) {

src/main/scala/rocket/rocc.scala

@@ -6,7 +6,7 @@ import Chisel._
 import uncore.tilelink._
 import uncore.constants._
 import uncore.agents.CacheName
-import Util._
+import util._
 import cde.{Parameters, Field}
 
 case object RoccMaxTaggedMemXacts extends Field[Int]

src/main/scala/rocket/rocket.scala

@@ -7,8 +7,7 @@ import uncore.devices._
 import uncore.agents.CacheName
 import uncore.constants._
 import junctions.HasAddrMapParameters
-import util.ParameterizedBundle
-import Util._
+import util._
 import cde.{Parameters, Field}
 
 case object XLen extends Field[Int]

src/main/scala/rocket/rvc.scala

@@ -2,9 +2,8 @@ package rocket
 
 import Chisel._
 import Chisel.ImplicitConversions._
-import Util._
+import util._
 import cde.Parameters
-import uncore.util._
 
 class ExpandedInstruction extends Bundle {
   val bits = UInt(width = 32)

src/main/scala/rocket/tile.scala

@@ -7,7 +7,7 @@ import uncore.tilelink._
 import uncore.agents._
 import uncore.converters._
 import uncore.devices._
-import Util._
+import util._
 import cde.{Parameters, Field}
 
 case object BuildRoCC extends Field[Seq[RoccParameters]]

src/main/scala/rocket/tlb.scala

@@ -3,13 +3,12 @@
 package rocket
 
 import Chisel._
-import Util._
+import util._
 import junctions._
 import scala.math._
 import cde.{Parameters, Field}
 import uncore.agents.PseudoLRU
 import uncore.coherence._
-import uncore.util._
 
 case object PgLevels extends Field[Int]
 case object ASIdBits extends Field[Int]

src/main/scala/rocket/util.scala

@@ -1,177 +0,0 @@
-// See LICENSE for license details.
-
-package rocket
-
-import Chisel._
-import uncore.util._
-import scala.math._
-import cde.{Parameters, Field}
-
-object Util {
-  implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
-  implicit def intToUInt(x: Int): UInt = UInt(x)
-  implicit def bigIntToUInt(x: BigInt): UInt = UInt(x)
-  implicit def booleanToBool(x: Boolean): Bits = Bool(x)
-  implicit def intSeqToUIntSeq(x: Seq[Int]): Seq[UInt] = x.map(UInt(_))
-  implicit def wcToUInt(c: WideCounter): UInt = c.value
-
-  implicit class UIntToAugmentedUInt(val x: UInt) extends AnyVal {
-    def sextTo(n: Int): UInt =
-      if (x.getWidth == n) x
-      else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
-
-    def extract(hi: Int, lo: Int): UInt = {
-      if (hi == lo-1) UInt(0)
-      else x(hi, lo)
-    }
-  }
-
-  implicit class BooleanToAugmentedBoolean(val x: Boolean) extends AnyVal {
-    def toInt: Int = if (x) 1 else 0
-
-    // this one's snagged from scalaz
-    def option[T](z: => T): Option[T] = if (x) Some(z) else None
-  }
-}
-
-object MuxT {
-  def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
-    (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
-
-  def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
-    (Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
-}
-
-import Util._
-
-object Str
-{
-  def apply(s: String): UInt = {
-    var i = BigInt(0)
-    require(s.forall(validChar _))
-    for (c <- s)
-      i = (i << 8) | c
-    UInt(i, s.length*8)
-  }
-  def apply(x: Char): UInt = {
-    require(validChar(x))
-    UInt(x.toInt, 8)
-  }
-  def apply(x: UInt): UInt = apply(x, 10)
-  def apply(x: UInt, radix: Int): UInt = {
-    val rad = UInt(radix)
-    val w = x.getWidth
-    require(w > 0)
-
-    var q = x
-    var s = digit(q % rad)
-    for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
-      q = q / rad
-      s = Cat(Mux(Bool(radix == 10) && q === UInt(0), Str(' '), digit(q % rad)), s)
-    }
-    s
-  }
-  def apply(x: SInt): UInt = apply(x, 10)
-  def apply(x: SInt, radix: Int): UInt = {
-    val neg = x < SInt(0)
-    val abs = x.abs
-    if (radix != 10) {
-      Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
-    } else {
-      val rad = UInt(radix)
-      val w = abs.getWidth
-      require(w > 0)
-
-      var q = abs
-      var s = digit(q % rad)
-      var needSign = neg
-      for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
-        q = q / rad
-        val placeSpace = q === UInt(0)
-        val space = Mux(needSign, Str('-'), Str(' '))
-        needSign = needSign && !placeSpace
-        s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
-      }
-      Cat(Mux(needSign, Str('-'), Str(' ')), s)
-    }
-  }
-
-  private def digit(d: UInt): UInt = Mux(d < UInt(10), Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
-  private def validChar(x: Char) = x == (x & 0xFF)
-}
-
-object Split
-{
-  // is there a better way to do do this?
-  def apply(x: Bits, n0: Int) = {
-    val w = checkWidth(x, n0)
-    (x(w-1,n0), x(n0-1,0))
-  }
-  def apply(x: Bits, n1: Int, n0: Int) = {
-    val w = checkWidth(x, n1, n0)
-    (x(w-1,n1), x(n1-1,n0), x(n0-1,0))
-  }
-  def apply(x: Bits, n2: Int, n1: Int, n0: Int) = {
-    val w = checkWidth(x, n2, n1, n0)
-    (x(w-1,n2), x(n2-1,n1), x(n1-1,n0), x(n0-1,0))
-  }
-
-  private def checkWidth(x: Bits, n: Int*) = {
-    val w = x.getWidth
-    def decreasing(x: Seq[Int]): Boolean =
-      if (x.tail.isEmpty) true
-      else x.head >= x.tail.head && decreasing(x.tail)
-    require(decreasing(w :: n.toList))
-    w
-  }
-}
-
-// a counter that clock gates most of its MSBs using the LSB carry-out
-case class WideCounter(width: Int, inc: UInt = UInt(1), reset: Boolean = true)
-{
-  private val isWide = width > 2*inc.getWidth
-  private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
-  private val small = if (reset) Reg(init=UInt(0, smallWidth)) else Reg(UInt(width = smallWidth))
-  private val nextSmall = small +& inc
-  small := nextSmall
-
-  private val large = if (isWide) {
-    val r = if (reset) Reg(init=UInt(0, width - smallWidth)) else Reg(UInt(width = width - smallWidth))
-    when (nextSmall(smallWidth)) { r := r +& UInt(1) }
-    r
-  } else null
-
-  val value = if (isWide) Cat(large, small) else small
-  lazy val carryOut = {
-    val lo = (small ^ nextSmall) >> 1
-    if (!isWide) lo else {
-      val hi = Mux(nextSmall(smallWidth), large ^ (large +& UInt(1)), UInt(0)) >> 1
-      Cat(hi, lo)
-    }
-  }
-
-  def := (x: UInt) = {
-    small := x
-    if (isWide) large := x >> smallWidth
-  }
-}
-
-object Random
-{
-  def apply(mod: Int, random: UInt): UInt = {
-    if (isPow2(mod)) random(log2Up(mod)-1,0)
-    else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
-  }
-  def apply(mod: Int): UInt = apply(mod, randomizer)
-  def oneHot(mod: Int, random: UInt): UInt = {
-    if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
-    else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
-  }
-  def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
-
-  private def randomizer = LFSR16()
-  private def round(x: Double): Int =
-    if (x.toInt.toDouble == x) x.toInt else (x.toInt + 1) & -2
-  private def partition(value: UInt, slices: Int) =
-    Seq.tabulate(slices)(i => value < round((i << value.getWidth).toDouble / slices))
-}