Move a bunch more things into util package
A lot of utility code was just being imported willy-nilly from one package to another. This moves the common code into util to make things more sensible. The code moved were * The AsyncQueue and AsyncDecoupledCrossing from junctions. * All of the code in rocket's util.scala * The BlackBox asynchronous reset registers from uncore.tilelink2 * The implicit definitions from uncore.util
This commit is contained in:
Howard Mao
@ -1,102 +0,0 @@
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// See LICENSE for license details.
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package junctions
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import Chisel._
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import uncore.util.{AsyncResetRegVec, AsyncResetReg}
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object GrayCounter {
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def apply(bits: Int, increment: Bool = Bool(true)): UInt = {
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val incremented = Wire(UInt(width=bits))
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val binary = AsyncResetReg(incremented, 0)
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incremented := binary + increment.asUInt()
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incremented ^ (incremented >> UInt(1))
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}
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}
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object AsyncGrayCounter {
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def apply(in: UInt, sync: Int): UInt = {
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val syncv = List.fill(sync)(Module (new AsyncResetRegVec(w = in.getWidth, 0)))
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syncv.last.io.d := in
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syncv.last.io.en := Bool(true)
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(syncv.init zip syncv.tail).foreach { case (sink, source) => {
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sink.io.d := source.io.q
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sink.io.en := Bool(true)
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}
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}
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syncv(0).io.d
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}
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}
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class AsyncQueueSource[T <: Data](gen: T, depth: Int, sync: Int, clockIn: Clock, resetIn: Bool)
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extends Module(_clock = clockIn, _reset = resetIn) {
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val bits = log2Ceil(depth)
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val io = new Bundle {
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// These come from the source domain
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val enq = Decoupled(gen).flip()
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// These cross to the sink clock domain
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val ridx = UInt(INPUT, width = bits+1)
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val widx = UInt(OUTPUT, width = bits+1)
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val mem = Vec(depth, gen).asOutput
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}
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val mem = Reg(Vec(depth, gen)) //This does NOT need to be asynchronously reset.
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val widx = GrayCounter(bits+1, io.enq.fire())
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val ridx = AsyncGrayCounter(io.ridx, sync)
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val ready = widx =/= (ridx ^ UInt(depth | depth >> 1))
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val index = if (depth == 1) UInt(0) else io.widx(bits-1, 0) ^ (io.widx(bits, bits) << (bits-1))
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when (io.enq.fire() && !reset) { mem(index) := io.enq.bits }
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val ready_reg = AsyncResetReg(ready, 0)
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io.enq.ready := ready_reg
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val widx_reg = AsyncResetReg(widx, 0)
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io.widx := widx_reg
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io.mem := mem
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}
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class AsyncQueueSink[T <: Data](gen: T, depth: Int, sync: Int, clockIn: Clock, resetIn: Bool)
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extends Module(_clock = clockIn, _reset = resetIn) {
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val bits = log2Ceil(depth)
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val io = new Bundle {
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// These come from the sink domain
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val deq = Decoupled(gen)
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// These cross to the source clock domain
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val ridx = UInt(OUTPUT, width = bits+1)
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val widx = UInt(INPUT, width = bits+1)
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val mem = Vec(depth, gen).asInput
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}
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val ridx = GrayCounter(bits+1, io.deq.fire())
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val widx = AsyncGrayCounter(io.widx, sync)
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val valid = ridx =/= widx
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// The mux is safe because timing analysis ensures ridx has reached the register
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// On an ASIC, changes to the unread location cannot affect the selected value
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// On an FPGA, only one input changes at a time => mem updates don't cause glitches
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// The register only latches when the selected valued is not being written
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val index = if (depth == 1) UInt(0) else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
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// This register does not NEED to be reset, as its contents will not
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// be considered unless the asynchronously reset deq valid register is set.
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io.deq.bits := RegEnable(io.mem(index), valid)
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io.deq.valid := AsyncResetReg(valid, 0)
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io.ridx := AsyncResetReg(ridx, 0)
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}
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class AsyncQueue[T <: Data](gen: T, depth: Int = 8, sync: Int = 3) extends Crossing[T] {
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require (sync >= 2)
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require (depth > 0 && isPow2(depth))
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val io = new CrossingIO(gen)
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val source = Module(new AsyncQueueSource(gen, depth, sync, io.enq_clock, io.enq_reset))
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val sink = Module(new AsyncQueueSink (gen, depth, sync, io.deq_clock, io.deq_reset))
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source.io.enq <> io.enq
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io.deq <> sink.io.deq
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sink.io.mem := source.io.mem
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sink.io.widx := source.io.widx
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source.io.ridx := sink.io.ridx
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}
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@ -1,134 +0,0 @@
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package junctions
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import Chisel._
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import chisel3.util.{DecoupledIO, Decoupled, Irrevocable, IrrevocableIO, ReadyValidIO}
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class CrossingIO[T <: Data](gen: T) extends Bundle {
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// Enqueue clock domain
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val enq_clock = Clock(INPUT)
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val enq_reset = Bool(INPUT) // synchronously deasserted wrt. enq_clock
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val enq = Decoupled(gen).flip()
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// Dequeue clock domain
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val deq_clock = Clock(INPUT)
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val deq_reset = Bool(INPUT) // synchronously deasserted wrt. deq_clock
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val deq = Decoupled(gen)
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}
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abstract class Crossing[T <: Data] extends Module {
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val io: CrossingIO[T]
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}
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class AsyncScope extends Module { val io = new Bundle }
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object AsyncScope { def apply() = Module(new AsyncScope) }
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object AsyncDecoupledCrossing
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{
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// takes from_source from the 'from' clock domain and puts it into the 'to' clock domain
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def apply[T <: Data](from_clock: Clock, from_reset: Bool, from_source: ReadyValidIO[T], to_clock: Clock, to_reset: Bool, depth: Int = 8, sync: Int = 3): DecoupledIO[T] = {
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val crossing = Module(new AsyncQueue(from_source.bits, depth, sync)).io
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crossing.enq_clock := from_clock
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crossing.enq_reset := from_reset
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crossing.enq <> from_source
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crossing.deq_clock := to_clock
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crossing.deq_reset := to_reset
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crossing.deq
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}
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}
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object AsyncDecoupledTo
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{
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// takes source from your clock domain and puts it into the 'to' clock domain
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def apply[T <: Data](to_clock: Clock, to_reset: Bool, source: ReadyValidIO[T], depth: Int = 8, sync: Int = 3): DecoupledIO[T] = {
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val scope = AsyncScope()
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AsyncDecoupledCrossing(scope.clock, scope.reset, source, to_clock, to_reset, depth, sync)
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}
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}
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object AsyncDecoupledFrom
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{
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// takes from_source from the 'from' clock domain and puts it into your clock domain
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def apply[T <: Data](from_clock: Clock, from_reset: Bool, from_source: ReadyValidIO[T], depth: Int = 8, sync: Int = 3): DecoupledIO[T] = {
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val scope = AsyncScope()
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AsyncDecoupledCrossing(from_clock, from_reset, from_source, scope.clock, scope.reset, depth, sync)
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}
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}
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object PostQueueIrrevocablize
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{
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def apply[T <: Data](deq: DecoupledIO[T]): IrrevocableIO[T] = {
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val irr = Wire(new IrrevocableIO(deq.bits))
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irr.bits := deq.bits
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irr.valid := deq.valid
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deq.ready := irr.ready
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irr
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}
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}
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object AsyncIrrevocableCrossing {
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def apply[T <: Data](from_clock: Clock, from_reset: Bool, from_source: ReadyValidIO[T], to_clock: Clock, to_reset: Bool, depth: Int = 8, sync: Int = 3): IrrevocableIO[T] = {
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PostQueueIrrevocablize(AsyncDecoupledCrossing(from_clock, from_reset, from_source, to_clock, to_reset, depth, sync))
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}
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}
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object AsyncIrrevocableTo
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{
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// takes source from your clock domain and puts it into the 'to' clock domain
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def apply[T <: Data](to_clock: Clock, to_reset: Bool, source: ReadyValidIO[T], depth: Int = 8, sync: Int = 3): IrrevocableIO[T] = {
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PostQueueIrrevocablize(AsyncDecoupledTo(to_clock, to_reset, source, depth, sync))
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}
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}
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object AsyncIrrevocableFrom
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{
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// takes from_source from the 'from' clock domain and puts it into your clock domain
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def apply[T <: Data](from_clock: Clock, from_reset: Bool, from_source: ReadyValidIO[T], depth: Int = 8, sync: Int = 3): IrrevocableIO[T] = {
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PostQueueIrrevocablize(AsyncDecoupledFrom(from_clock, from_reset, from_source, depth, sync))
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}
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}
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/**
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* This helper object synchronizes a level-sensitive signal from one
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* clock domain to another.
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*/
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object LevelSyncCrossing {
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class SynchronizerBackend(sync: Int, _clock: Clock) extends Module(Some(_clock)) {
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val io = new Bundle {
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val in = Bool(INPUT)
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val out = Bool(OUTPUT)
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}
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io.out := ShiftRegister(io.in, sync)
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}
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class SynchronizerFrontend(_clock: Clock) extends Module(Some(_clock)) {
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val io = new Bundle {
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val in = Bool(INPUT)
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val out = Bool(OUTPUT)
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}
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io.out := RegNext(io.in)
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}
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def apply(from_clock: Clock, to_clock: Clock, in: Bool, sync: Int = 2): Bool = {
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val front = Module(new SynchronizerFrontend(from_clock))
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val back = Module(new SynchronizerBackend(sync, to_clock))
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front.io.in := in
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back.io.in := front.io.out
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back.io.out
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}
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}
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object LevelSyncTo {
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def apply(to_clock: Clock, in: Bool, sync: Int = 2): Bool = {
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val scope = AsyncScope()
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LevelSyncCrossing(scope.clock, to_clock, in, sync)
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}
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}
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object LevelSyncFrom {
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def apply(from_clock: Clock, in: Bool, sync: Int = 2): Bool = {
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val scope = AsyncScope()
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LevelSyncCrossing(from_clock, scope.clock, in, sync)
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}
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}
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@ -4,7 +4,7 @@ package junctions
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import Chisel._
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import scala.math.max
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import scala.collection.mutable.ArraySeq
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import util.{ParameterizedBundle, HellaPeekingArbiter}
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import util._
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import cde.{Parameters, Field}
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case object NastiKey extends Field[NastiParameters]
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Block a user