riscv/rocket-chip
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fix fpu port direction bug

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This commit is contained in:
Andrew Waterman
2012-02-08 15:19:08 -08:00
parent b3f6f9a5fd
commit 990e3a1b34
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/fpu.scala
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@@ -120,7 +120,7 @@ class rocketFPU extends Component
val killx = Bool(INPUT)
val killm = Bool(INPUT)
val dmem = new ioDmem(List("resp_val", "resp_tag", "resp_data"))
val dmem = new ioDmem(List("resp_val", "resp_tag", "resp_data")).flip()
val dpath = new ioDpathFPU().flip()
}