From 98eede05050ec9d71798e991b009e3b68dd7e855 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 1 Aug 2016 11:02:59 -0700 Subject: [PATCH] some refactoring in RocketChip top-level --- src/main/scala/RocketChip.scala | 86 ++++++++++++++++++++------------- 1 file changed, 53 insertions(+), 33 deletions(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index d21fe702..716294fe 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -140,28 +140,6 @@ object TopUtils { outer.acquire <> Queue(inner.acquire) inner.grant <> Queue(outer.grant) } - def makeBootROM()(implicit p: Parameters) = { - val rom = java.nio.ByteBuffer.allocate(32) - rom.order(java.nio.ByteOrder.LITTLE_ENDIAN) - - // for now, have the reset vector jump straight to memory - val resetToMemDist = p(GlobalAddrMap)("mem").start - p(ResetVector) - require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12)) - val configStringAddr = p(ResetVector).toInt + rom.capacity - - // This boot ROM doesn't know about any boot devices, so it just spins, - // waiting for the debugger to load a program and change the PC. - rom.putInt(0x0000006f) // loop forever - rom.putInt(0) // reserved - rom.putInt(0) // reserved - rom.putInt(configStringAddr) // pointer to config string - rom.putInt(0) // default trap vector - rom.putInt(0) // ... - rom.putInt(0) // ... - rom.putInt(0) // ... - - rom.array() ++ p(ConfigString).toSeq - } } /** Top-level module for the chip */ @@ -187,8 +165,8 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters { val uncore = Module(new Uncore()(innerTLParams)) - uncore.io.prci.zip(tileResets).zip(tileList).foreach { - case ((prci, rst), tile) => + (uncore.io.prci, tileResets, tileList).zipped.foreach { + case (prci, rst, tile) => rst := prci.reset tile.io.prci <> prci } @@ -198,19 +176,38 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters { uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten uncore.io.interrupts <> io.interrupts uncore.io.debugBus <> - (if (p(AsyncDebugBus)) AsyncDebugBusFrom(io.debug_clk.get, io.debug_rst.get, io.debug) else io.debug) + (if (p(AsyncDebugBus)) + AsyncDebugBusFrom(io.debug_clk.get, io.debug_rst.get, io.debug) + else io.debug) - for (i <- 0 until p(NExtMMIOAXIChannels)) - io.mmio_axi(i) <> (if (p(AsyncMMIOChannels)) AsyncNastiTo((io.mmio_clk.get)(i), (io.mmio_rst.get)(i), uncore.io.mmio_axi(i)) else uncore.io.mmio_axi(i)) + def asyncAxiTo(clocks: Seq[Clock], resets: Seq[Bool], inner_axis: Seq[NastiIO]): Seq[NastiIO] = + (clocks, resets, inner_axis).zipped.map { + case (clk, rst, in_axi) => AsyncNastiTo(clk, rst, in_axi) + } + + def asyncAxiFrom(clocks: Seq[Clock], resets: Seq[Bool], outer_axis: Seq[NastiIO]): Seq[NastiIO] = + (clocks, resets, outer_axis).zipped.map { + case (clk, rst, out_axi) => AsyncNastiFrom(clk, rst, out_axi) + } + + io.mmio_axi <> + (if (p(AsyncMMIOChannels)) + asyncAxiTo(io.mmio_clk.get, io.mmio_rst.get, uncore.io.mmio_axi) + else uncore.io.mmio_axi) io.mmio_ahb <> uncore.io.mmio_ahb io.mmio_tl <> uncore.io.mmio_tl - - for (i <- 0 until nMemAXIChannels) - io.mem_axi(i) <> (if (p(AsyncMemChannels)) AsyncNastiTo((io.mem_clk.get)(i), (io.mem_rst.get)(i), uncore.io.mem_axi(i)) else uncore.io.mem_axi(i)) + + io.mem_axi <> + (if (p(AsyncMemChannels)) + asyncAxiTo(io.mem_clk.get, io.mem_rst.get, uncore.io.mem_axi) + else uncore.io.mem_axi) io.mem_ahb <> uncore.io.mem_ahb io.mem_tl <> uncore.io.mem_tl - for (i <- 0 until p(NExtBusAXIChannels)) - uncore.io.bus_axi(i) <> (if (p(AsyncDebugBus)) AsyncNastiFrom((io.bus_clk.get)(i), (io.bus_rst.get)(i), io.bus_axi(i)) else io.bus_axi(i)) + + uncore.io.bus_axi <> + (if (p(AsyncBusChannels)) + asyncAxiFrom(io.bus_clk.get, io.bus_rst.get, io.bus_axi) + else io.bus_axi) } /** Wrapper around everything that isn't a Tile. @@ -273,6 +270,29 @@ class Uncore(implicit val p: Parameters) extends Module } } + def makeBootROM()(implicit p: Parameters) = { + val rom = java.nio.ByteBuffer.allocate(32) + rom.order(java.nio.ByteOrder.LITTLE_ENDIAN) + + // for now, have the reset vector jump straight to memory + val resetToMemDist = p(GlobalAddrMap)("mem").start - p(ResetVector) + require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12)) + val configStringAddr = p(ResetVector).toInt + rom.capacity + + // This boot ROM doesn't know about any boot devices, so it just spins, + // waiting for the debugger to load a program and change the PC. + rom.putInt(0x0000006f) // loop forever + rom.putInt(0) // reserved + rom.putInt(0) // reserved + rom.putInt(configStringAddr) // pointer to config string + rom.putInt(0) // default trap vector + rom.putInt(0) // ... + rom.putInt(0) // ... + rom.putInt(0) // ... + + rom.array() ++ p(ConfigString).toSeq + } + def buildMMIONetwork(implicit p: Parameters) = { val ioAddrMap = p(GlobalAddrMap).subMap("io") @@ -305,7 +325,7 @@ class Uncore(implicit val p: Parameters) extends Module io.prci(i).reset := reset } - val bootROM = Module(new ROMSlave(TopUtils.makeBootROM())) + val bootROM = Module(new ROMSlave(makeBootROM())) bootROM.io <> mmioNetwork.port("int:bootrom") // The memory map presently has only one external I/O region