riscv/rocket-chip
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Prevent some unnecessary pipeline replays

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This commit is contained in:
Andrew Waterman
2017-11-06 11:04:06 -08:00
parent c8bc487ab8
commit 989eeb78f9
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/rocket/IBuf.scala
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@@ -60,9 +60,9 @@ class IBuf(implicit p: Parameters) extends CoreModule {
buf := io.imem.bits
buf.data := shiftInsnRight(io.imem.bits.data, shamt)(n*coreInstBits-1,0)
buf.pc := io.imem.bits.pc & ~pcWordMask | (io.imem.bits.pc + (nICReady << log2Ceil(coreInstBytes))) & pcWordMask
ibufBTBHit := io.imem.bits.btb.valid
ibufBTBHit := io.imem.bits.btb.valid && io.imem.bits.btb.bits.bridx >= shamt
ibufBTBResp := io.imem.bits.btb.bits
ibufBTBResp.bridx := io.imem.bits.btb.bits.bridx + nICReady
ibufBTBResp.bridx := io.imem.bits.btb.bits.bridx - shamt
}
}
when (io.kill) {