diff --git a/src/main/scala/coreplex/CoreplexNetwork.scala b/src/main/scala/coreplex/CoreplexNetwork.scala
index 811620f1..3ee9a279 100644
--- a/src/main/scala/coreplex/CoreplexNetwork.scala
+++ b/src/main/scala/coreplex/CoreplexNetwork.scala
@@ -26,11 +26,18 @@ trait CoreplexNetwork extends HasCoreplexParameters {
   val mmio = TLOutputNode()
   val mmioInt = IntInputNode()
   val l2in = TLInputNode()
+  val l2out = TLOutputNode()
 
   intBar.intnode := mmioInt
 
   // Allows a variable number of inputs from outside to the Xbar
-  l1tol2.node :=* l2in
+  private val l2in_buffer = LazyModule(new TLBuffer)
+  l1tol2.node :=* l2in_buffer.node
+  l2in_buffer.node :=* l2in
+
+  private val l2out_buffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none))
+  l2out :*= l2out_buffer.node
+  l2out_buffer.node :*= l1tol2.node
 
   cbus.node :=
     TLBuffer()(
@@ -96,6 +103,7 @@ trait CoreplexNetworkBundle extends HasCoreplexParameters {
   val mmio = outer.mmio.bundleOut
   val interrupts = outer.mmioInt.bundleIn
   val l2in = outer.l2in.bundleIn
+  val l2out = outer.l2out.bundleOut
 }
 
 trait CoreplexNetworkModule extends HasCoreplexParameters {
@@ -130,7 +138,7 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
     val node = TLOutputNode()
     for (bank <- 0 until l2Config.nBanksPerChannel) {
       val offset = (bank * l2Config.nMemoryChannels) + channel
-      in := TLBuffer(BufferParams.flow)(l1tol2.node)
+      in := TLBuffer(BufferParams.flow, BufferParams.none)(l1tol2.node)
       node := TLFilter(AddressSet(offset * l1tol2_lineBytes, mask))(out)
     }
     node
diff --git a/src/main/scala/rocketchip/BaseTop.scala b/src/main/scala/rocketchip/BaseTop.scala
index 7e2638d3..d74c8499 100644
--- a/src/main/scala/rocketchip/BaseTop.scala
+++ b/src/main/scala/rocketchip/BaseTop.scala
@@ -36,7 +36,8 @@ trait HasTopLevelNetworks extends HasPeripheryParameters {
   val socBus = LazyModule(new TLXbar)          // Wide or unordered-access slave devices (TL-UH)
   val peripheryBus = LazyModule(new TLXbar)    // Narrow and ordered-access slave devices (TL-UL)
   val intBus = LazyModule(new IntXbar)         // Interrupts
-  val l2FrontendBus = LazyModule(new TLBuffer) // Master devices talking to the frontside of the L2
+  val fsb = LazyModule(new TLBuffer(BufferParams.none))          // Master devices talking to the frontside of the L2
+  val bsb = LazyModule(new TLBuffer(BufferParams.none))          // Slave devices talking to the backside of the L2
   val mem = Seq.fill(nMemoryChannels) { LazyModule(new TLXbar) } // Ports out to DRAM
 
   // The peripheryBus hangs off of socBus;
diff --git a/src/main/scala/rocketchip/Periphery.scala b/src/main/scala/rocketchip/Periphery.scala
index 4b1776ea..b5b9cc48 100644
--- a/src/main/scala/rocketchip/Periphery.scala
+++ b/src/main/scala/rocketchip/Periphery.scala
@@ -214,7 +214,7 @@ trait PeripherySlaveAXI4 extends HasTopLevelNetworks {
     masters = Seq(AXI4MasterParameters(
       id = IdRange(0, 1 << config.idBits))))))
 
-  l2FrontendBus.node :=
+  fsb.node :=
     TLSourceShrinker(1 << config.sourceBits)(
     TLWidthWidget(config.beatBytes)(
     AXI4ToTL()(
@@ -282,7 +282,7 @@ trait PeripherySlaveTL extends HasTopLevelNetworks {
     clients = Seq(TLClientParameters(
       sourceId = IdRange(0, 1 << config.idBits))))))
 
-  l2FrontendBus.node :=
+  fsb.node :=
     TLSourceShrinker(1 << config.sourceBits)(
     TLWidthWidget(config.beatBytes)(
     l2FrontendTLNode))
diff --git a/src/main/scala/rocketchip/RocketPlexMaster.scala b/src/main/scala/rocketchip/RocketPlexMaster.scala
index 8d2bf546..d0a31dd1 100644
--- a/src/main/scala/rocketchip/RocketPlexMaster.scala
+++ b/src/main/scala/rocketchip/RocketPlexMaster.scala
@@ -15,7 +15,8 @@ trait RocketPlexMaster extends HasTopLevelNetworks {
 
   val coreplex = LazyModule(new DefaultCoreplex)
 
-  coreplex.l2in :=* l2FrontendBus.node
+  coreplex.l2in :=* fsb.node
+  bsb.node :*= coreplex.l2out
   socBus.node := coreplex.mmio
   coreplex.mmioInt := intBus.intnode