riscv/rocket-chip
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For Rockets without VM, widen vaddrBits to paddrBits

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This supports addressing a >39-bit physical address space.
This commit is contained in:
Andrew Waterman
2017-10-07 17:33:36 -07:00
parent a0e5a20b60
commit 986cbfb6b1
3 changed files with 21 additions and 13 deletions
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11
src/main/scala/tile/BaseTile.scala
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@@ -42,7 +42,14 @@ trait HasTileParameters {
def iLen: Int = 32
def pgIdxBits: Int = 12
def pgLevelBits: Int = 10 - log2Ceil(xLen / 32)
def vaddrBits: Int = pgIdxBits + pgLevels * pgLevelBits
def vaddrBits: Int =
if (usingVM) {
val v = pgIdxBits + pgLevels * pgLevelBits
require(v == xLen || xLen > v && v > paddrBits)
v
} else {
paddrBits min xLen
}
def paddrBits: Int = p(SharedMemoryTLEdge).bundle.addressBits
def vpnBits: Int = vaddrBits - pgIdxBits
def ppnBits: Int = paddrBits - pgIdxBits
@@ -53,7 +60,7 @@ trait HasTileParameters {
def maxPAddrBits: Int = xLen match { case 32 => 34; case 64 => 56 }
def hartIdLen: Int = p(MaxHartIdBits)
def resetVectorLen: Int = paddrBits min vaddrBitsExtended
def resetVectorLen: Int = paddrBits
def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + tileParams.rocc.size
}