riscv/rocket-chip
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Merge pull request #28 from ucb-bar/yusnup

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Don't re-generate the .d files on "make clean"
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Colin Schmidt 2015-11-12 00:46:21 -08:00
commit 97d0e195ae
2 changed files with 4 additions and 0 deletions
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2
emulator/Makefile
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@ -70,7 +70,9 @@ test:
# Run assembly tests and benchmarks # Run assembly tests and benchmarks
#-------------------------------------------------------------------- #--------------------------------------------------------------------
ifneq ($(MAKECMDGOALS),clean)
-include $(generated_dir)/$(MODEL).$(CONFIG).d -include $(generated_dir)/$(MODEL).$(CONFIG).d
endif
$(output_dir)/%.run: $(output_dir)/%.hex emulator-$(MODEL)-$(CONFIG) $(output_dir)/%.run: $(output_dir)/%.hex emulator-$(MODEL)-$(CONFIG)
./$(emu) +dramsim +max-cycles=$(timeout_cycles) +loadmem=$< none 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ] ./$(emu) +dramsim +max-cycles=$(timeout_cycles) +loadmem=$< none 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]

2
vsim/Makefile
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@ -21,7 +21,9 @@ TB ?= rocketTestHarness
include $(base_dir)/Makefrag include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag include $(sim_dir)/Makefrag
ifneq ($(MAKECMDGOALS),clean)
-include $(generated_dir)/$(MODEL).$(CONFIG).d -include $(generated_dir)/$(MODEL).$(CONFIG).d
endif
include $(base_dir)/vsim/Makefrag-verilog include $(base_dir)/vsim/Makefrag-verilog
all: $(simv) all: $(simv)