now depend on external cde library rather than chisel.params (bump all submodules)

Makefrag

@@ -11,7 +11,7 @@ CXXFLAGS := -O1
 SBT := java -Xmx2048M -Xss8M -XX:MaxPermSize=128M -jar sbt-launch.jar
 SHELL := /bin/bash
 
-CHISEL_ARGS := $(MODEL) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configInstance $(PROJECT).$(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
+CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
 
 src_path = src/main/scala
 default_submodules = . junctions uncore hardfloat rocket zscale

chisel

@@ -1 +1 @@
-Subproject commit d3e0c01512b61cf4755b1d6b99b7e8865514689a
+Subproject commit be810b7d47f07c461caae67fe9cc52ee05c15b78

context-dependent-environments

@@ -1 +1 @@
-Subproject commit b199196e8c2b2920b683f501b15c404fe63124c2
+Subproject commit 62cf74d84e1bfd456ff967c321fd612d94f015be

junctions

@@ -1 +1 @@
-Subproject commit 624da311ac1af900f4f21c74385eade6ac29f9e7
+Subproject commit 965403e5a567101171098296d6db770c10ebc7cb

project/build.scala

@@ -16,10 +16,11 @@ object BuildSettings extends Build {
   )
 
   lazy val chisel    = project
+  lazy val cde       = project in file("context-dependent-environments")
   lazy val hardfloat = project.dependsOn(chisel)
-  lazy val junctions = project.dependsOn(chisel)
+  lazy val junctions = project.dependsOn(chisel, cde)
   lazy val uncore    = project.dependsOn(junctions)
-  lazy val rocket    = project.dependsOn(hardfloat,uncore)
+  lazy val rocket    = project.dependsOn(hardfloat, uncore)
   lazy val zscale    = project.dependsOn(rocket)
   lazy val rocketchip = (project in file(".")).settings(chipSettings).dependsOn(zscale)
 

rocket

@@ -1 +1 @@
-Subproject commit d1eae61970f864afe4fde8ca7f75380c70c4658f
+Subproject commit 45dd153d55cbcfd4c491d603213a54f8ef8e6c76

src/main/scala/Configs.scala

@@ -10,8 +10,9 @@ import rocket.Util._
 import zscale._
 import scala.math.max
 import DefaultTestSuites._
+import cde.{Parameters, Config, Dump, Knob}
 
-class DefaultConfig extends ChiselConfig (
+class DefaultConfig extends Config (
   topDefinitions = { (pname,site,here) => 
     type PF = PartialFunction[Any,Any]
     def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
@@ -176,15 +177,15 @@ class DefaultConfig extends ChiselConfig (
 class DefaultVLSIConfig extends DefaultConfig
 class DefaultCPPConfig extends DefaultConfig
 
-class With2Cores extends ChiselConfig(knobValues = { case "NTILES" => 2 })
+class With2Cores extends Config(knobValues = { case "NTILES" => 2 })
-class With4Cores extends ChiselConfig(knobValues = { case "NTILES" => 4 })
+class With4Cores extends Config(knobValues = { case "NTILES" => 4 })
-class With8Cores extends ChiselConfig(knobValues = { case "NTILES" => 8 })
+class With8Cores extends Config(knobValues = { case "NTILES" => 8 })
 
-class With2Banks extends ChiselConfig(knobValues = { case "NBANKS" => 2 })
+class With2Banks extends Config(knobValues = { case "NBANKS" => 2 })
-class With4Banks extends ChiselConfig(knobValues = { case "NBANKS" => 4 })
+class With4Banks extends Config(knobValues = { case "NBANKS" => 4 })
-class With8Banks extends ChiselConfig(knobValues = { case "NBANKS" => 8 })
+class With8Banks extends Config(knobValues = { case "NBANKS" => 8 })
 
-class WithL2Cache extends ChiselConfig(
+class WithL2Cache extends Config(
   (pname,site,here) => pname match {
     case "L2_CAPACITY_IN_KB" => Knob("L2_CAPACITY_IN_KB")
     case "L2Bank" => {
@@ -207,19 +208,19 @@ class WithL2Cache extends ChiselConfig(
   knobValues = { case "L2_WAYS" => 8; case "L2_CAPACITY_IN_KB" => 2048 }
 )
 
-class WithL2Capacity2048 extends ChiselConfig(knobValues = { case "L2_CAPACITY_IN_KB" => 2048 })
+class WithL2Capacity2048 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 2048 })
-class WithL2Capacity1024 extends ChiselConfig(knobValues = { case "L2_CAPACITY_IN_KB" => 1024 })
+class WithL2Capacity1024 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 1024 })
-class WithL2Capacity512 extends ChiselConfig(knobValues = { case "L2_CAPACITY_IN_KB" => 512 })
+class WithL2Capacity512 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 512 })
-class WithL2Capacity256 extends ChiselConfig(knobValues = { case "L2_CAPACITY_IN_KB" => 256 })
+class WithL2Capacity256 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 256 })
-class WithL2Capacity128 extends ChiselConfig(knobValues = { case "L2_CAPACITY_IN_KB" => 128 })
+class WithL2Capacity128 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 128 })
-class WithL2Capacity64 extends ChiselConfig(knobValues = { case "L2_CAPACITY_IN_KB" => 64 })
+class WithL2Capacity64 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 64 })
 
-class DefaultL2Config extends ChiselConfig(new WithL2Cache ++ new DefaultConfig)
+class DefaultL2Config extends Config(new WithL2Cache ++ new DefaultConfig)
-class DefaultL2VLSIConfig extends ChiselConfig(new WithL2Cache ++ new DefaultVLSIConfig)
+class DefaultL2VLSIConfig extends Config(new WithL2Cache ++ new DefaultVLSIConfig)
-class DefaultL2CPPConfig extends ChiselConfig(new WithL2Cache ++ new DefaultCPPConfig)
+class DefaultL2CPPConfig extends Config(new WithL2Cache ++ new DefaultCPPConfig)
-class DefaultL2FPGAConfig extends ChiselConfig(new WithL2Capacity64 ++ new WithL2Cache ++ new DefaultFPGAConfig)
+class DefaultL2FPGAConfig extends Config(new WithL2Capacity64 ++ new WithL2Cache ++ new DefaultFPGAConfig)
 
-class WithZscale extends ChiselConfig(
+class WithZscale extends Config(
   (pname,site,here) => pname match {
     case BuildZscale => {
       TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
@@ -232,18 +233,18 @@ class WithZscale extends ChiselConfig(
   }
 )
 
-class ZscaleConfig extends ChiselConfig(new WithZscale ++ new DefaultConfig)
+class ZscaleConfig extends Config(new WithZscale ++ new DefaultConfig)
 
-class FPGAConfig extends ChiselConfig (
+class FPGAConfig extends Config (
   (pname,site,here) => pname match {
     case NAcquireTransactors => 4
     case UseBackupMemoryPort => false
   }
 )
 
-class DefaultFPGAConfig extends ChiselConfig(new FPGAConfig ++ new DefaultConfig)
+class DefaultFPGAConfig extends Config(new FPGAConfig ++ new DefaultConfig)
 
-class SmallConfig extends ChiselConfig (
+class SmallConfig extends Config (
     topDefinitions = { (pname,site,here) => pname match {
       case UseFPU => false
       case FastMulDiv => false
@@ -258,10 +259,10 @@ class SmallConfig extends ChiselConfig (
   }
 )
 
-class DefaultFPGASmallConfig extends ChiselConfig(new SmallConfig ++ new DefaultFPGAConfig)
+class DefaultFPGASmallConfig extends Config(new SmallConfig ++ new DefaultFPGAConfig)
 
-class ExampleSmallConfig extends ChiselConfig(new SmallConfig ++ new DefaultConfig)
+class ExampleSmallConfig extends Config(new SmallConfig ++ new DefaultConfig)
 
-class MultibankConfig extends ChiselConfig(new With2Banks ++ new DefaultConfig)
+class MultibankConfig extends Config(new With2Banks ++ new DefaultConfig)
-class MultibankL2Config extends ChiselConfig(
+class MultibankL2Config extends Config(
   new With2Banks ++ new WithL2Cache ++ new DefaultConfig)

src/main/scala/Network.scala

@@ -4,6 +4,7 @@ package rocketchip
 
 import Chisel._
 import uncore._
+import cde.Parameters
 
 /** RocketChipNetworks combine a TileLink protocol with a particular physical
   * network implementation and chip layout.

src/main/scala/RocketChip.scala

@@ -3,6 +3,7 @@
 package rocketchip
 
 import Chisel._
+import cde.{Parameters, Field}
 import junctions._
 import uncore._
 import rocket._
@@ -77,8 +78,8 @@ class MultiChannelTopIO(implicit p: Parameters) extends BasicTopIO()(p) {
 
 /** Top-level module for the chip */
 //TODO: Remove this wrapper once multichannel DRAM controller is provided
-class Top extends Module with HasTopLevelParameters {
+class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
-  implicit val p = params
+  implicit val p = topParams
   val io = new TopIO
   if(!p(UseZscale)) {
     val temp = Module(new MultiChannelTop)

src/main/scala/Testing.scala

@@ -4,6 +4,7 @@ package rocketchip
 
 import Chisel._
 import scala.collection.mutable.LinkedHashSet
+import cde.{Parameters, ParameterDump, Config}
 
 abstract class RocketTestSuite {
   val dir: String
@@ -52,7 +53,7 @@ object TestGeneration extends FileSystemUtilities{
   
   def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }
 
-  def generateMakefrag {
+  def generateMakefrag(topModuleName: String, configClassName: String) {
     def gen(kind: String, s: Seq[RocketTestSuite]) = {
       if(s.length > 0) {
         val targets = s.map(t => s"$$(${t.makeTargetName})").mkString(" ") 
@@ -67,8 +68,12 @@ run-$kind-tests-fast: $$(addprefix $$(output_dir)/, $$(addsuffix .run, $targets)
       } else { "\n" }
     }
 
-    val f = createOutputFile(s"${Driver.topComponent.get.name}.${Driver.chiselConfigClassName.get}.d")
+    val f = createOutputFile(s"$topModuleName.$configClassName.d")
-    f.write(List(gen("asm", asmSuites.values.toSeq), gen("bmark", bmarkSuites.values.toSeq)).mkString("\n"))
+    f.write(
+      List(
+        gen("asm", asmSuites.values.toSeq),
+        gen("bmark", bmarkSuites.values.toSeq)
+      ).mkString("\n"))
     f.close
   }
 }
@@ -123,8 +128,31 @@ object DefaultTestSuites {
     "led", "mbist"))
 }
 
-object TestGenerator extends App {
+object TestGenerator extends App with FileSystemUtilities {
-  val gen = () => Class.forName("rocketchip."+args(0)).newInstance().asInstanceOf[Module]
+  val projectName = args(0)
-  chiselMain.run(args.drop(1), gen)
+  val topModuleName = args(1)
-  TestGeneration.generateMakefrag
+  val configClassName = args(2)
+  val config = try {
+      Class.forName(s"$projectName.$configClassName").newInstance.asInstanceOf[Config]
+    } catch {
+      case e: java.lang.ClassNotFoundException =>
+        throwException(s"Could not find the cde.Config subclass you asked for " +
+                        "(i.e. \"$configClassName\"), did you misspell it?", e)
+    }
+  val paramsFromConfig: Parameters = Parameters.root(config.toInstance)
+
+  val gen = () => 
+    Class.forName(s"$projectName.$topModuleName")
+      .getConstructor(classOf[cde.Parameters])
+      .newInstance(paramsFromConfig)
+      .asInstanceOf[Module]
+
+  chiselMain.run(args.drop(3), gen)
+  //Driver.elaborate(gen, configName = configClassName)
+
+  TestGeneration.generateMakefrag(topModuleName, configClassName)
+
+  val pdFile = createOutputFile(s"$topModuleName.$configClassName.prm")
+  pdFile.write(ParameterDump.getDump)
+  pdFile.close
 }

src/main/scala/Vlsi.scala

@@ -3,11 +3,12 @@
 package rocketchip
 
 import Chisel._
+import cde.Parameters
 import junctions._
 import uncore._
 
-class MemDessert extends Module {
+class MemDessert(topParams: Parameters) extends Module {
-  implicit val p = params
+  implicit val p = topParams
   val io = new MemDesserIO(p(HtifKey).width)
   val x = Module(new MemDesser(p(HtifKey).width))
   io.narrow <> x.io.narrow

src/main/scala/ZscaleChip.scala

@@ -3,6 +3,7 @@
 package rocketchip
 
 import Chisel._
+import cde.{Parameters, Field}
 import junctions._
 import uncore._
 import rocket._

uncore

@@ -1 +1 @@
-Subproject commit ce01a9bbf02fa982d1c2520a595f3e2427662846
+Subproject commit 5348eb49c0880123a8fcb1ab1a838491002d8ffb

vsim/Makefrag-verilog

@@ -16,7 +16,7 @@ $(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).v
 	echo "\`endif // CONST_VH" >> $@
 
 $(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
-	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run MemDessert --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)"
+	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(PROJECT) MemDessert $(CONFIG) --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configName $(CONFIG)"
 
 #--------------------------------------------------------------------
 # Run

zscale

@@ -1 +1 @@
-Subproject commit d6cc2dc512f93be328578e79798ee13510eb4c72
+Subproject commit 77c779d473cc82963383691e16d0151045c1c936