riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

now depend on external cde library rather than chisel.params (bump all submodules)

Browse Source
This commit is contained in:
Henry Cook
2015-10-21 18:23:58 -07:00
parent 47bc193c16
commit 9769b2747c
15 changed files with 82 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
vsim/Makefrag-verilog
View File

@ -16,7 +16,7 @@ $(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).v
echo "\`endif // CONST_VH" >> $@
$(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run MemDessert --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)"
cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(PROJECT) MemDessert $(CONFIG) --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configName $(CONFIG)"
#--------------------------------------------------------------------
# Run