uncore: switch to new diplomacy Node API
Most adapters should work on multiple ports. This patch changes them all.
This commit is contained in:
Wesley W. Terpstra
@ -18,8 +18,8 @@ class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, p
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require (r >= 0)
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val node = AXI4AdapterNode(
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masterFn = { case Seq(p) => p },
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slaveFn = { case Seq(p) => p.copy(minLatency = p.minLatency + min(1,min(aw,ar)) + min(1,min(r,b))) })
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masterFn = { p => p },
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slaveFn = { p => p.copy(minLatency = p.minLatency + min(1,min(aw,ar)) + min(1,min(r,b))) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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@ -23,8 +23,8 @@ class AXI4Fragmenter(lite: Boolean = false, maxInFlight: => Int = 32, combinatio
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def mapMaster(m: AXI4MasterParameters) = m.copy(aligned = true)
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val node = AXI4AdapterNode(
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masterFn = { case Seq(mp) => mp.copy(masters = mp.masters.map(m => mapMaster(m))) },
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slaveFn = { case Seq(sp) => sp.copy(slaves = sp.slaves .map(s => mapSlave(s, sp.beatBytes))) })
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masterFn = { mp => mp.copy(masters = mp.masters.map(m => mapMaster(m))) },
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slaveFn = { sp => sp.copy(slaves = sp.slaves .map(s => mapSlave(s, sp.beatBytes))) })
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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@ -32,256 +32,253 @@ class AXI4Fragmenter(lite: Boolean = false, maxInFlight: => Int = 32, combinatio
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val out = node.bundleOut
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}
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val edgeOut = node.edgesOut(0)
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val edgeIn = node.edgesIn(0)
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val slave = edgeOut.slave
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val slaves = slave.slaves
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val beatBytes = slave.beatBytes
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val lgBytes = log2Ceil(beatBytes)
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val master = edgeIn.master
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val masters = master.masters
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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val slave = edgeOut.slave
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val slaves = slave.slaves
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val beatBytes = slave.beatBytes
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val lgBytes = log2Ceil(beatBytes)
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val master = edgeIn.master
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val masters = master.masters
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// If the user claimed this was a lite interface, then there must be only one Id
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require (!lite || master.endId == 1)
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// If the user claimed this was a lite interface, then there must be only one Id
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require (!lite || master.endId == 1)
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// We don't support fragmenting to sub-beat accesses
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slaves.foreach { s =>
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require (!s.supportsRead || s.supportsRead.contains(beatBytes))
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require (!s.supportsWrite || s.supportsWrite.contains(beatBytes))
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}
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// We don't support fragmenting to sub-beat accesses
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slaves.foreach { s =>
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require (!s.supportsRead || s.supportsRead.contains(beatBytes))
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require (!s.supportsWrite || s.supportsWrite.contains(beatBytes))
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}
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/* We need to decompose a request into
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* FIXED => each beat is a new request
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* WRAP/INCR => take xfr up to next power of two, capped by max size of target
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*
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* On AR and AW, we fragment one request into many
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* On W we set 'last' on beats which are fragment boundaries
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* On R we clear 'last' on the fragments being reassembled
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* On B we clear 'valid' on the responses for the injected fragments
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*
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* AR=>R and AW+W=>B are completely independent state machines.
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*/
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/* Returns the number of beats to execute and the new address */
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def fragment(a: IrrevocableIO[AXI4BundleA], supportedSizes1: Seq[Int]): (IrrevocableIO[AXI4BundleA], Bool, UInt) = {
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val out = Wire(a)
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val busy = RegInit(Bool(false))
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val r_addr = Reg(UInt(width = a.bits.params.addrBits))
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val r_len = Reg(UInt(width = AXI4Parameters.lenBits))
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val len = Mux(busy, r_len, a.bits.len)
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val addr = Mux(busy, r_addr, a.bits.addr)
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val lo = if (lgBytes == 0) UInt(0) else addr(lgBytes-1, 0)
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val hi = addr >> lgBytes
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val alignment = hi(AXI4Parameters.lenBits-1,0)
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val allSame = supportedSizes1.filter(_ >= 0).distinct.size <= 1
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val dynamic1 = Mux1H(slave.findFast(addr), supportedSizes1.map(s => UInt(max(0, s))))
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val fixed1 = UInt(supportedSizes1.filter(_ >= 0).headOption.getOrElse(0))
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/* We need to compute the largest transfer allowed by the AXI len.
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* len+1 is the number of beats to execute.
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* We want the MSB(len+1)-1; one less than the largest power of two we could execute.
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* There are two cases; either len is 2^n-1 in which case we leave it unchanged, ELSE
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* fill the bits from highest to lowest, and shift right by one bit.
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/* We need to decompose a request into
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* FIXED => each beat is a new request
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* WRAP/INCR => take xfr up to next power of two, capped by max size of target
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*
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* On AR and AW, we fragment one request into many
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* On W we set 'last' on beats which are fragment boundaries
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* On R we clear 'last' on the fragments being reassembled
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* On B we clear 'valid' on the responses for the injected fragments
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*
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* AR=>R and AW+W=>B are completely independent state machines.
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*/
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val fillLow = rightOR(len) >> 1 // set all bits in positions < a set bit
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val wipeHigh = ~leftOR(~len) // clear all bits in position >= a cleared bit
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val remain1 = fillLow | wipeHigh // MSB(a.len+1)-1
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val align1 = ~leftOR(alignment) // transfer size limited by address alignment
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val support1 = if (allSame) fixed1 else dynamic1 // maximum supported size-1 based on target address
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val maxSupported1 = remain1 & align1 & support1 // Take the minimum of all the limits
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// Things that cause us to degenerate to a single beat
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val fixed = a.bits.burst === AXI4Parameters.BURST_FIXED
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val narrow = a.bits.size =/= UInt(lgBytes)
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val bad = fixed || narrow
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/* Returns the number of beats to execute and the new address */
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def fragment(a: IrrevocableIO[AXI4BundleA], supportedSizes1: Seq[Int]): (IrrevocableIO[AXI4BundleA], Bool, UInt) = {
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val out = Wire(a)
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// The number of beats-1 to execute
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val beats1 = Mux(bad, UInt(0), maxSupported1)
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val beats = OH1ToOH(beats1) // beats1 + 1
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val busy = RegInit(Bool(false))
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val r_addr = Reg(UInt(width = a.bits.params.addrBits))
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val r_len = Reg(UInt(width = AXI4Parameters.lenBits))
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val inc_addr = addr + (beats << a.bits.size) // address after adding transfer
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val wrapMask = a.bits.bytes1() // only these bits may change, if wrapping
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val mux_addr = Wire(init = inc_addr)
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when (a.bits.burst === AXI4Parameters.BURST_WRAP) {
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mux_addr := (inc_addr & wrapMask) | ~(~a.bits.addr | wrapMask)
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}
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when (a.bits.burst === AXI4Parameters.BURST_FIXED) {
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mux_addr := a.bits.addr
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val len = Mux(busy, r_len, a.bits.len)
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val addr = Mux(busy, r_addr, a.bits.addr)
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val lo = if (lgBytes == 0) UInt(0) else addr(lgBytes-1, 0)
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val hi = addr >> lgBytes
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val alignment = hi(AXI4Parameters.lenBits-1,0)
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val allSame = supportedSizes1.filter(_ >= 0).distinct.size <= 1
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val dynamic1 = Mux1H(slave.findFast(addr), supportedSizes1.map(s => UInt(max(0, s))))
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val fixed1 = UInt(supportedSizes1.filter(_ >= 0).headOption.getOrElse(0))
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/* We need to compute the largest transfer allowed by the AXI len.
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* len+1 is the number of beats to execute.
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* We want the MSB(len+1)-1; one less than the largest power of two we could execute.
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* There are two cases; either len is 2^n-1 in which case we leave it unchanged, ELSE
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* fill the bits from highest to lowest, and shift right by one bit.
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*/
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val fillLow = rightOR(len) >> 1 // set all bits in positions < a set bit
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val wipeHigh = ~leftOR(~len) // clear all bits in position >= a cleared bit
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val remain1 = fillLow | wipeHigh // MSB(a.len+1)-1
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val align1 = ~leftOR(alignment) // transfer size limited by address alignment
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val support1 = if (allSame) fixed1 else dynamic1 // maximum supported size-1 based on target address
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val maxSupported1 = remain1 & align1 & support1 // Take the minimum of all the limits
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// Things that cause us to degenerate to a single beat
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val fixed = a.bits.burst === AXI4Parameters.BURST_FIXED
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val narrow = a.bits.size =/= UInt(lgBytes)
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val bad = fixed || narrow
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// The number of beats-1 to execute
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val beats1 = Mux(bad, UInt(0), maxSupported1)
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val beats = OH1ToOH(beats1) // beats1 + 1
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val inc_addr = addr + (beats << a.bits.size) // address after adding transfer
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val wrapMask = a.bits.bytes1() // only these bits may change, if wrapping
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val mux_addr = Wire(init = inc_addr)
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when (a.bits.burst === AXI4Parameters.BURST_WRAP) {
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mux_addr := (inc_addr & wrapMask) | ~(~a.bits.addr | wrapMask)
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}
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when (a.bits.burst === AXI4Parameters.BURST_FIXED) {
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mux_addr := a.bits.addr
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}
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val last = beats1 === len
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a.ready := out.ready && last
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out.valid := a.valid
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out.bits := a.bits
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out.bits.len := beats1
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// We forcibly align every access. If the first beat was misaligned, the strb bits
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// for the lower addresses must not have been set. Therefore, rounding the address
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// down is harmless. We can do this after the address update algorithm, because the
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// incremented values will be rounded down the same way. Furthermore, a subword
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// offset cannot cause a premature wrap-around.
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out.bits.addr := ~(~addr | UIntToOH1(a.bits.size, lgBytes))
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when (out.fire()) {
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busy := !last
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r_addr := mux_addr
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r_len := len - beats
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}
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(out, last, beats)
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}
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val last = beats1 === len
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a.ready := out.ready && last
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out.valid := a.valid
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// The size to which we will fragment the access
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val readSizes1 = slaves.map(s => s.supportsRead .max/beatBytes-1)
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val writeSizes1 = slaves.map(s => s.supportsWrite.max/beatBytes-1)
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out.bits := a.bits
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out.bits.len := beats1
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// Indirection variables for inputs and outputs; makes transformation application easier
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val (in_ar, ar_last, _) = fragment(Queue.irrevocable(in.ar, 1, flow=true), readSizes1)
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val (in_aw, aw_last, w_beats) = fragment(Queue.irrevocable(in.aw, 1, flow=true), writeSizes1)
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val in_w = in.w
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val in_r = in.r
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val in_b = in.b
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val out_ar = Wire(out.ar)
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val out_aw = out.aw
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val out_w = out.w
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val out_r = Wire(out.r)
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val out_b = Wire(out.b)
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// We forcibly align every access. If the first beat was misaligned, the strb bits
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// for the lower addresses must not have been set. Therefore, rounding the address
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// down is harmless. We can do this after the address update algorithm, because the
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// incremented values will be rounded down the same way. Furthermore, a subword
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// offset cannot cause a premature wrap-around.
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out.bits.addr := ~(~addr | UIntToOH1(a.bits.size, lgBytes))
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when (out.fire()) {
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busy := !last
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r_addr := mux_addr
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r_len := len - beats
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val depth = if (combinational) 1 else 2
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// In case a slave ties arready := rready, we need a queue to break the combinational loop
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// between the two branches (in_ar => {out_ar => out_r, sideband} => in_r).
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if (in.ar.bits.getWidth < in.r.bits.getWidth) {
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out.ar <> Queue(out_ar, depth, flow=combinational)
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out_r <> out.r
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} else {
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out.ar <> out_ar
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out_r <> Queue(out.r, depth, flow=combinational)
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}
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// In case a slave ties awready := bready or wready := bready, we need this queue
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out_b <> Queue(out.b, depth, flow=combinational)
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(out, last, beats)
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}
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// Sideband to track which transfers were the last fragment
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def sideband() = if (lite) {
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Module(new Queue(Bool(), maxInFlight, flow=combinational)).io
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} else {
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Module(new AXI4FragmenterSideband(maxInFlight, flow=combinational)).io
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}
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val sideband_ar_r = sideband()
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val sideband_aw_b = sideband()
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val in = io.in(0)
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val out = io.out(0)
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// AR flow control
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out_ar.valid := in_ar.valid && sideband_ar_r.enq.ready
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in_ar.ready := sideband_ar_r.enq.ready && out_ar.ready
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sideband_ar_r.enq.valid := in_ar.valid && out_ar.ready
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out_ar.bits := in_ar.bits
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sideband_ar_r.enq.bits := ar_last
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// The size to which we will fragment the access
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val readSizes1 = slaves.map(s => s.supportsRead .max/beatBytes-1)
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val writeSizes1 = slaves.map(s => s.supportsWrite.max/beatBytes-1)
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// When does W channel start counting a new transfer
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val wbeats_latched = RegInit(Bool(false))
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val wbeats_ready = Wire(Bool())
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val wbeats_valid = Wire(Bool())
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when (wbeats_valid && wbeats_ready) { wbeats_latched := Bool(true) }
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when (out_aw.fire()) { wbeats_latched := Bool(false) }
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// Indirection variables for inputs and outputs; makes transformation application easier
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val (in_ar, ar_last, _) = fragment(Queue.irrevocable(in.ar, 1, flow=true), readSizes1)
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val (in_aw, aw_last, w_beats) = fragment(Queue.irrevocable(in.aw, 1, flow=true), writeSizes1)
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val in_w = in.w
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val in_r = in.r
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val in_b = in.b
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val out_ar = Wire(out.ar)
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val out_aw = out.aw
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val out_w = out.w
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val out_r = Wire(out.r)
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val out_b = Wire(out.b)
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// AW flow control
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out_aw.valid := in_aw.valid && sideband_aw_b.enq.ready && (wbeats_ready || wbeats_latched)
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in_aw.ready := sideband_aw_b.enq.ready && out_aw.ready && (wbeats_ready || wbeats_latched)
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sideband_aw_b.enq.valid := in_aw.valid && out_aw.ready && (wbeats_ready || wbeats_latched)
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wbeats_valid := in_aw.valid && !wbeats_latched
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out_aw.bits := in_aw.bits
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sideband_aw_b.enq.bits := aw_last
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val depth = if (combinational) 1 else 2
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// In case a slave ties arready := rready, we need a queue to break the combinational loop
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// between the two branches (in_ar => {out_ar => out_r, sideband} => in_r).
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if (in.ar.bits.getWidth < in.r.bits.getWidth) {
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out.ar <> Queue(out_ar, depth, flow=combinational)
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out_r <> out.r
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} else {
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out.ar <> out_ar
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out_r <> Queue(out.r, depth, flow=combinational)
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}
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// In case a slave ties awready := bready or wready := bready, we need this queue
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out_b <> Queue(out.b, depth, flow=combinational)
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// We need to inject 'last' into the W channel fragments, count!
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val w_counter = RegInit(UInt(0, width = AXI4Parameters.lenBits+1))
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val w_idle = w_counter === UInt(0)
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val w_todo = Mux(w_idle, Mux(wbeats_valid, w_beats, UInt(0)), w_counter)
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val w_last = w_todo === UInt(1)
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w_counter := w_todo - out_w.fire()
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assert (!out_w.fire() || w_todo =/= UInt(0)) // underflow impossible
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// Sideband to track which transfers were the last fragment
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def sideband() = if (lite) {
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Module(new Queue(Bool(), maxInFlight, flow=combinational)).io
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} else {
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Module(new AXI4FragmenterSideband(maxInFlight, flow=combinational)).io
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}
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val sideband_ar_r = sideband()
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val sideband_aw_b = sideband()
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// W flow control
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wbeats_ready := w_idle
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out_w.valid := in_w.valid && (!wbeats_ready || wbeats_valid)
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in_w.ready := out_w.ready && (!wbeats_ready || wbeats_valid)
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out_w.bits := in_w.bits
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out_w.bits.last := w_last
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// We should also recreate the last last
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assert (!out_w.valid || !in_w.bits.last || w_last)
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// AR flow control
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out_ar.valid := in_ar.valid && sideband_ar_r.enq.ready
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in_ar.ready := sideband_ar_r.enq.ready && out_ar.ready
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sideband_ar_r.enq.valid := in_ar.valid && out_ar.ready
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out_ar.bits := in_ar.bits
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sideband_ar_r.enq.bits := ar_last
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// R flow control
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val r_last = out_r.bits.last
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in_r.valid := out_r.valid && (!r_last || sideband_ar_r.deq.valid)
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out_r.ready := in_r.ready && (!r_last || sideband_ar_r.deq.valid)
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sideband_ar_r.deq.ready := r_last && out_r.valid && in_r.ready
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in_r.bits := out_r.bits
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in_r.bits.last := r_last && sideband_ar_r.deq.bits
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// When does W channel start counting a new transfer
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val wbeats_latched = RegInit(Bool(false))
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val wbeats_ready = Wire(Bool())
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val wbeats_valid = Wire(Bool())
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when (wbeats_valid && wbeats_ready) { wbeats_latched := Bool(true) }
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when (out_aw.fire()) { wbeats_latched := Bool(false) }
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// B flow control
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val b_last = sideband_aw_b.deq.bits
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in_b.valid := out_b.valid && sideband_aw_b.deq.valid && b_last
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out_b.ready := sideband_aw_b.deq.valid && (!b_last || in_b.ready)
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sideband_aw_b.deq.ready := out_b.valid && (!b_last || in_b.ready)
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in_b.bits := out_b.bits
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// AW flow control
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out_aw.valid := in_aw.valid && sideband_aw_b.enq.ready && (wbeats_ready || wbeats_latched)
|
||||
in_aw.ready := sideband_aw_b.enq.ready && out_aw.ready && (wbeats_ready || wbeats_latched)
|
||||
sideband_aw_b.enq.valid := in_aw.valid && out_aw.ready && (wbeats_ready || wbeats_latched)
|
||||
wbeats_valid := in_aw.valid && !wbeats_latched
|
||||
out_aw.bits := in_aw.bits
|
||||
sideband_aw_b.enq.bits := aw_last
|
||||
|
||||
// We need to inject 'last' into the W channel fragments, count!
|
||||
val w_counter = RegInit(UInt(0, width = AXI4Parameters.lenBits+1))
|
||||
val w_idle = w_counter === UInt(0)
|
||||
val w_todo = Mux(w_idle, Mux(wbeats_valid, w_beats, UInt(0)), w_counter)
|
||||
val w_last = w_todo === UInt(1)
|
||||
w_counter := w_todo - out_w.fire()
|
||||
assert (!out_w.fire() || w_todo =/= UInt(0)) // underflow impossible
|
||||
|
||||
// W flow control
|
||||
wbeats_ready := w_idle
|
||||
out_w.valid := in_w.valid && (!wbeats_ready || wbeats_valid)
|
||||
in_w.ready := out_w.ready && (!wbeats_ready || wbeats_valid)
|
||||
out_w.bits := in_w.bits
|
||||
out_w.bits.last := w_last
|
||||
// We should also recreate the last last
|
||||
assert (!out_w.valid || !in_w.bits.last || w_last)
|
||||
|
||||
// R flow control
|
||||
val r_last = out_r.bits.last
|
||||
in_r.valid := out_r.valid && (!r_last || sideband_ar_r.deq.valid)
|
||||
out_r.ready := in_r.ready && (!r_last || sideband_ar_r.deq.valid)
|
||||
sideband_ar_r.deq.ready := r_last && out_r.valid && in_r.ready
|
||||
in_r.bits := out_r.bits
|
||||
in_r.bits.last := r_last && sideband_ar_r.deq.bits
|
||||
|
||||
// B flow control
|
||||
val b_last = sideband_aw_b.deq.bits
|
||||
in_b.valid := out_b.valid && sideband_aw_b.deq.valid && b_last
|
||||
out_b.ready := sideband_aw_b.deq.valid && (!b_last || in_b.ready)
|
||||
sideband_aw_b.deq.ready := out_b.valid && (!b_last || in_b.ready)
|
||||
in_b.bits := out_b.bits
|
||||
|
||||
// Merge errors from dropped B responses
|
||||
val r_resp = RegInit(UInt(0, width = AXI4Parameters.respBits))
|
||||
val resp = out_b.bits.resp | r_resp
|
||||
when (out_b.fire()) { r_resp := Mux(b_last, UInt(0), resp) }
|
||||
in_b.bits.resp := resp
|
||||
}
|
||||
}
|
||||
|
||||
/* We want to put barriers between the fragments of a fragmented transfer and all other transfers.
|
||||
* This lets us use very little state to reassemble the fragments (else we need one FIFO per ID).
|
||||
* Furthermore, because all the fragments share the same AXI ID, they come back contiguously.
|
||||
* This guarantees that no other R responses might get mixed between fragments, ensuring that the
|
||||
* interleavedId for the slaves remains unaffected by the fragmentation transformation.
|
||||
* Of course, if you need to fragment, this means there is a potentially hefty serialization cost.
|
||||
* However, this design allows full concurrency in the common no-fragmentation-needed scenario.
|
||||
*/
|
||||
class AXI4FragmenterSideband(maxInFlight: Int, flow: Boolean = false) extends Module
|
||||
{
|
||||
val io = new QueueIO(Bool(), maxInFlight)
|
||||
io.count := UInt(0)
|
||||
|
||||
val PASS = UInt(2, width = 2) // allow 'last=1' bits to enque, on 'last=0' if count>0 block else accept+FIND
|
||||
val FIND = UInt(0, width = 2) // allow 'last=0' bits to enque, accept 'last=1' and switch to WAIT
|
||||
val WAIT = UInt(1, width = 2) // block all access till count=0
|
||||
|
||||
val state = RegInit(PASS)
|
||||
val count = RegInit(UInt(0, width = log2Up(maxInFlight)))
|
||||
val full = count === UInt(maxInFlight-1)
|
||||
val empty = count === UInt(0)
|
||||
val last = count === UInt(1)
|
||||
|
||||
io.deq.bits := state(1) || (last && state(0)) // PASS || (last && WAIT)
|
||||
io.deq.valid := !empty
|
||||
|
||||
io.enq.ready := !full && (empty || (state === FIND) || (state === PASS && io.enq.bits))
|
||||
|
||||
// WAIT => count > 0
|
||||
assert (state =/= WAIT || count =/= UInt(0))
|
||||
|
||||
if (flow) {
|
||||
when (io.enq.valid) {
|
||||
io.deq.valid := Bool(true)
|
||||
when (empty) { io.deq.bits := io.enq.bits }
|
||||
// Merge errors from dropped B responses
|
||||
val r_resp = RegInit(UInt(0, width = AXI4Parameters.respBits))
|
||||
val resp = out_b.bits.resp | r_resp
|
||||
when (out_b.fire()) { r_resp := Mux(b_last, UInt(0), resp) }
|
||||
in_b.bits.resp := resp
|
||||
}
|
||||
}
|
||||
|
||||
count := count + io.enq.fire() - io.deq.fire()
|
||||
switch (state) {
|
||||
is(PASS) { when (io.enq.valid && !io.enq.bits && empty) { state := FIND } }
|
||||
is(FIND) { when (io.enq.valid && io.enq.bits && !full) { state := Mux(empty, PASS, WAIT) } }
|
||||
is(WAIT) { when (last && io.deq.ready) { state := PASS } }
|
||||
/* We want to put barriers between the fragments of a fragmented transfer and all other transfers.
|
||||
* This lets us use very little state to reassemble the fragments (else we need one FIFO per ID).
|
||||
* Furthermore, because all the fragments share the same AXI ID, they come back contiguously.
|
||||
* This guarantees that no other R responses might get mixed between fragments, ensuring that the
|
||||
* interleavedId for the slaves remains unaffected by the fragmentation transformation.
|
||||
* Of course, if you need to fragment, this means there is a potentially hefty serialization cost.
|
||||
* However, this design allows full concurrency in the common no-fragmentation-needed scenario.
|
||||
*/
|
||||
class AXI4FragmenterSideband(maxInFlight: Int, flow: Boolean = false) extends Module
|
||||
{
|
||||
val io = new QueueIO(Bool(), maxInFlight)
|
||||
io.count := UInt(0)
|
||||
|
||||
val PASS = UInt(2, width = 2) // allow 'last=1' bits to enque, on 'last=0' if count>0 block else accept+FIND
|
||||
val FIND = UInt(0, width = 2) // allow 'last=0' bits to enque, accept 'last=1' and switch to WAIT
|
||||
val WAIT = UInt(1, width = 2) // block all access till count=0
|
||||
|
||||
val state = RegInit(PASS)
|
||||
val count = RegInit(UInt(0, width = log2Up(maxInFlight)))
|
||||
val full = count === UInt(maxInFlight-1)
|
||||
val empty = count === UInt(0)
|
||||
val last = count === UInt(1)
|
||||
|
||||
io.deq.bits := state(1) || (last && state(0)) // PASS || (last && WAIT)
|
||||
io.deq.valid := !empty
|
||||
|
||||
io.enq.ready := !full && (empty || (state === FIND) || (state === PASS && io.enq.bits))
|
||||
|
||||
// WAIT => count > 0
|
||||
assert (state =/= WAIT || count =/= UInt(0))
|
||||
|
||||
if (flow) {
|
||||
when (io.enq.valid) {
|
||||
io.deq.valid := Bool(true)
|
||||
when (empty) { io.deq.bits := io.enq.bits }
|
||||
}
|
||||
}
|
||||
|
||||
count := count + io.enq.fire() - io.deq.fire()
|
||||
switch (state) {
|
||||
is(PASS) { when (io.enq.valid && !io.enq.bits && empty) { state := FIND } }
|
||||
is(FIND) { when (io.enq.valid && io.enq.bits && !full) { state := Mux(empty, PASS, WAIT) } }
|
||||
is(WAIT) { when (last && io.deq.ready) { state := PASS } }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -31,16 +31,13 @@ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters
|
||||
|
||||
// Nodes implemented inside modules
|
||||
case class AXI4IdentityNode() extends IdentityNode(AXI4Imp)
|
||||
case class AXI4MasterNode(portParams: AXI4MasterPortParameters, numPorts: Range.Inclusive = 1 to 1)
|
||||
extends SourceNode(AXI4Imp)(portParams, numPorts)
|
||||
case class AXI4SlaveNode(portParams: AXI4SlavePortParameters, numPorts: Range.Inclusive = 1 to 1)
|
||||
extends SinkNode(AXI4Imp)(portParams, numPorts)
|
||||
case class AXI4MasterNode(portParams: Seq[AXI4MasterPortParameters]) extends SourceNode(AXI4Imp)(portParams)
|
||||
case class AXI4SlaveNode(portParams: Seq[AXI4SlavePortParameters]) extends SinkNode(AXI4Imp)(portParams)
|
||||
case class AXI4AdapterNode(
|
||||
masterFn: Seq[AXI4MasterPortParameters] => AXI4MasterPortParameters,
|
||||
slaveFn: Seq[AXI4SlavePortParameters] => AXI4SlavePortParameters,
|
||||
numMasterPorts: Range.Inclusive = 1 to 1,
|
||||
numSlavePorts: Range.Inclusive = 1 to 1)
|
||||
extends InteriorNode(AXI4Imp)(masterFn, slaveFn, numMasterPorts, numSlavePorts)
|
||||
masterFn: AXI4MasterPortParameters => AXI4MasterPortParameters,
|
||||
slaveFn: AXI4SlavePortParameters => AXI4SlavePortParameters,
|
||||
numPorts: Range.Inclusive = 0 to 999)
|
||||
extends AdapterNode(AXI4Imp)(masterFn, slaveFn, numPorts)
|
||||
|
||||
// Nodes passed from an inner module
|
||||
case class AXI4OutputNode() extends OutputNode(AXI4Imp)
|
||||
|
||||
@ -9,7 +9,7 @@ import regmapper._
|
||||
import scala.math.{min,max}
|
||||
|
||||
class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
|
||||
extends AXI4SlaveNode(AXI4SlavePortParameters(
|
||||
extends AXI4SlaveNode(Seq(AXI4SlavePortParameters(
|
||||
Seq(AXI4SlaveParameters(
|
||||
address = Seq(address),
|
||||
executable = executable,
|
||||
@ -17,7 +17,7 @@ class AXI4RegisterNode(address: AddressSet, concurrency: Int = 0, beatBytes: Int
|
||||
supportsRead = TransferSizes(1, beatBytes),
|
||||
interleavedId = Some(0))),
|
||||
beatBytes = beatBytes,
|
||||
minLatency = min(concurrency, 1))) // the Queue adds at most one cycle
|
||||
minLatency = min(concurrency, 1)))) // the Queue adds at most one cycle
|
||||
{
|
||||
require (address.contiguous)
|
||||
|
||||
|
||||
@ -8,7 +8,7 @@ import diplomacy._
|
||||
|
||||
class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = AXI4SlaveNode(AXI4SlavePortParameters(
|
||||
val node = AXI4SlaveNode(Seq(AXI4SlavePortParameters(
|
||||
Seq(AXI4SlaveParameters(
|
||||
address = List(address),
|
||||
regionType = RegionType.UNCACHED,
|
||||
@ -17,7 +17,7 @@ class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int =
|
||||
supportsWrite = TransferSizes(1, beatBytes),
|
||||
interleavedId = Some(0))),
|
||||
beatBytes = beatBytes,
|
||||
minLatency = 0)) // B responds on same cycle
|
||||
minLatency = 0))) // B responds on same cycle
|
||||
|
||||
// We require the address range to include an entire beat (for the write mask)
|
||||
require ((address.mask & (beatBytes-1)) == beatBytes-1)
|
||||
|
||||
@ -8,15 +8,15 @@ import config._
|
||||
import diplomacy._
|
||||
import uncore.tilelink2._
|
||||
|
||||
case class AXI4ToTLNode() extends MixedNode(AXI4Imp, TLImp)(
|
||||
dFn = { case (1, Seq(AXI4MasterPortParameters(masters))) =>
|
||||
Seq(TLClientPortParameters(clients = masters.map { m =>
|
||||
case class AXI4ToTLNode() extends MixedAdapterNode(AXI4Imp, TLImp)(
|
||||
dFn = { case AXI4MasterPortParameters(masters) =>
|
||||
TLClientPortParameters(clients = masters.map { m =>
|
||||
TLClientParameters(
|
||||
sourceId = IdRange(m.id.start << 1, m.id.end << 1), // R+W ids are distinct
|
||||
nodePath = m.nodePath)
|
||||
}))
|
||||
})
|
||||
},
|
||||
uFn = { case (1, Seq(mp)) => Seq(AXI4SlavePortParameters(
|
||||
uFn = { mp => AXI4SlavePortParameters(
|
||||
slaves = mp.managers.map { m =>
|
||||
AXI4SlaveParameters(
|
||||
address = m.address,
|
||||
@ -27,10 +27,8 @@ case class AXI4ToTLNode() extends MixedNode(AXI4Imp, TLImp)(
|
||||
supportsRead = m.supportsGet,
|
||||
interleavedId = Some(0))}, // TL2 never interleaves D beats
|
||||
beatBytes = mp.beatBytes,
|
||||
minLatency = mp.minLatency))
|
||||
},
|
||||
numPO = 1 to 1,
|
||||
numPI = 1 to 1)
|
||||
minLatency = mp.minLatency)
|
||||
})
|
||||
|
||||
class AXI4ToTL()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
@ -42,131 +40,129 @@ class AXI4ToTL()(implicit p: Parameters) extends LazyModule
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
val in = io.in(0)
|
||||
val out = io.out(0)
|
||||
val edgeIn = node.edgesIn(0)
|
||||
val edgeOut = node.edgesOut(0)
|
||||
val numIds = edgeIn.master.endId
|
||||
val beatBytes = edgeOut.manager.beatBytes
|
||||
val countBits = AXI4Parameters.lenBits + (1 << AXI4Parameters.sizeBits) - 1
|
||||
((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
|
||||
val numIds = edgeIn.master.endId
|
||||
val beatBytes = edgeOut.manager.beatBytes
|
||||
val countBits = AXI4Parameters.lenBits + (1 << AXI4Parameters.sizeBits) - 1
|
||||
|
||||
require (edgeIn.master.masters(0).aligned)
|
||||
require (edgeIn.master.masters(0).aligned)
|
||||
|
||||
val r_out = Wire(out.a)
|
||||
val r_inflight = RegInit(UInt(0, width = numIds))
|
||||
val r_block = r_inflight(in.ar.bits.id)
|
||||
val r_size1 = in.ar.bits.bytes1()
|
||||
val r_size = OH1ToUInt(r_size1)
|
||||
val r_addr = in.ar.bits.addr
|
||||
val r_ok = edgeOut.manager.supportsGetSafe(r_addr, r_size)
|
||||
val r_err_in = Wire(Decoupled(new AXI4BundleRError(in.ar.bits.params)))
|
||||
val r_err_out = Queue(r_err_in, 2)
|
||||
val r_count = RegInit(UInt(0, width = in.ar.bits.params.lenBits))
|
||||
val r_last = r_count === in.ar.bits.len
|
||||
val r_out = Wire(out.a)
|
||||
val r_inflight = RegInit(UInt(0, width = numIds))
|
||||
val r_block = r_inflight(in.ar.bits.id)
|
||||
val r_size1 = in.ar.bits.bytes1()
|
||||
val r_size = OH1ToUInt(r_size1)
|
||||
val r_addr = in.ar.bits.addr
|
||||
val r_ok = edgeOut.manager.supportsGetSafe(r_addr, r_size)
|
||||
val r_err_in = Wire(Decoupled(new AXI4BundleRError(in.ar.bits.params)))
|
||||
val r_err_out = Queue(r_err_in, 2)
|
||||
val r_count = RegInit(UInt(0, width = in.ar.bits.params.lenBits))
|
||||
val r_last = r_count === in.ar.bits.len
|
||||
|
||||
assert (!in.ar.valid || r_size1 === UIntToOH1(r_size, countBits)) // because aligned
|
||||
in.ar.ready := Mux(r_ok, r_out.ready, r_err_in.ready && r_last) && !r_block
|
||||
r_out.valid := in.ar.valid && !r_block && r_ok
|
||||
r_out.bits := edgeOut.Get(in.ar.bits.id << 1 | UInt(1), r_addr, r_size)._2
|
||||
r_err_in.valid := in.ar.valid && !r_block && !r_ok
|
||||
r_err_in.bits.last := r_last
|
||||
r_err_in.bits.id := in.ar.bits.id
|
||||
assert (!in.ar.valid || r_size1 === UIntToOH1(r_size, countBits)) // because aligned
|
||||
in.ar.ready := Mux(r_ok, r_out.ready, r_err_in.ready && r_last) && !r_block
|
||||
r_out.valid := in.ar.valid && !r_block && r_ok
|
||||
r_out.bits := edgeOut.Get(in.ar.bits.id << 1 | UInt(1), r_addr, r_size)._2
|
||||
r_err_in.valid := in.ar.valid && !r_block && !r_ok
|
||||
r_err_in.bits.last := r_last
|
||||
r_err_in.bits.id := in.ar.bits.id
|
||||
|
||||
when (r_err_in.fire()) { r_count := Mux(r_last, UInt(0), r_count + UInt(1)) }
|
||||
when (r_err_in.fire()) { r_count := Mux(r_last, UInt(0), r_count + UInt(1)) }
|
||||
|
||||
val w_out = Wire(out.a)
|
||||
val w_inflight = RegInit(UInt(0, width = numIds))
|
||||
val w_block = w_inflight(in.aw.bits.id)
|
||||
val w_size1 = in.aw.bits.bytes1()
|
||||
val w_size = OH1ToUInt(w_size1)
|
||||
val w_addr = in.aw.bits.addr
|
||||
val w_ok = edgeOut.manager.supportsPutPartialSafe(w_addr, w_size)
|
||||
val w_err_in = Wire(Decoupled(in.aw.bits.id))
|
||||
val w_err_out = Queue(w_err_in, 2)
|
||||
val w_out = Wire(out.a)
|
||||
val w_inflight = RegInit(UInt(0, width = numIds))
|
||||
val w_block = w_inflight(in.aw.bits.id)
|
||||
val w_size1 = in.aw.bits.bytes1()
|
||||
val w_size = OH1ToUInt(w_size1)
|
||||
val w_addr = in.aw.bits.addr
|
||||
val w_ok = edgeOut.manager.supportsPutPartialSafe(w_addr, w_size)
|
||||
val w_err_in = Wire(Decoupled(in.aw.bits.id))
|
||||
val w_err_out = Queue(w_err_in, 2)
|
||||
|
||||
assert (!in.aw.valid || w_size1 === UIntToOH1(w_size, countBits)) // because aligned
|
||||
assert (!in.aw.valid || in.aw.bits.len === UInt(0) || in.aw.bits.size === UInt(log2Ceil(beatBytes))) // because aligned
|
||||
in.aw.ready := Mux(w_ok, w_out.ready, w_err_in.ready) && in.w.valid && in.w.bits.last && !w_block
|
||||
in.w.ready := Mux(w_ok, w_out.ready, w_err_in.ready || !in.w.bits.last) && in.aw.valid && !w_block
|
||||
w_out.valid := in.aw.valid && in.w.valid && !w_block && w_ok
|
||||
w_out.bits := edgeOut.Put(in.aw.bits.id << 1, w_addr, w_size, in.w.bits.data, in.w.bits.strb)._2
|
||||
w_err_in.valid := in.aw.valid && in.w.valid && !w_block && !w_ok && in.w.bits.last
|
||||
w_err_in.bits := in.aw.bits.id
|
||||
assert (!in.aw.valid || w_size1 === UIntToOH1(w_size, countBits)) // because aligned
|
||||
assert (!in.aw.valid || in.aw.bits.len === UInt(0) || in.aw.bits.size === UInt(log2Ceil(beatBytes))) // because aligned
|
||||
in.aw.ready := Mux(w_ok, w_out.ready, w_err_in.ready) && in.w.valid && in.w.bits.last && !w_block
|
||||
in.w.ready := Mux(w_ok, w_out.ready, w_err_in.ready || !in.w.bits.last) && in.aw.valid && !w_block
|
||||
w_out.valid := in.aw.valid && in.w.valid && !w_block && w_ok
|
||||
w_out.bits := edgeOut.Put(in.aw.bits.id << 1, w_addr, w_size, in.w.bits.data, in.w.bits.strb)._2
|
||||
w_err_in.valid := in.aw.valid && in.w.valid && !w_block && !w_ok && in.w.bits.last
|
||||
w_err_in.bits := in.aw.bits.id
|
||||
|
||||
TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (UInt(0), r_out), (in.aw.bits.len, w_out))
|
||||
TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (UInt(0), r_out), (in.aw.bits.len, w_out))
|
||||
|
||||
val ok_b = Wire(in.b)
|
||||
val err_b = Wire(in.b)
|
||||
val mux_b = Wire(in.b)
|
||||
val ok_r = Wire(in.r)
|
||||
val err_r = Wire(in.r)
|
||||
val mux_r = Wire(in.r)
|
||||
val ok_b = Wire(in.b)
|
||||
val err_b = Wire(in.b)
|
||||
val mux_b = Wire(in.b)
|
||||
val ok_r = Wire(in.r)
|
||||
val err_r = Wire(in.r)
|
||||
val mux_r = Wire(in.r)
|
||||
|
||||
val d_resp = Mux(out.d.bits.error, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
|
||||
val d_hasData = edgeOut.hasData(out.d.bits)
|
||||
val d_last = edgeOut.last(out.d)
|
||||
val d_resp = Mux(out.d.bits.error, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
|
||||
val d_hasData = edgeOut.hasData(out.d.bits)
|
||||
val d_last = edgeOut.last(out.d)
|
||||
|
||||
out.d.ready := Mux(d_hasData, ok_r.ready, ok_b.ready)
|
||||
ok_r.valid := out.d.valid && d_hasData
|
||||
ok_b.valid := out.d.valid && !d_hasData
|
||||
out.d.ready := Mux(d_hasData, ok_r.ready, ok_b.ready)
|
||||
ok_r.valid := out.d.valid && d_hasData
|
||||
ok_b.valid := out.d.valid && !d_hasData
|
||||
|
||||
ok_r.bits.id := out.d.bits.source >> 1
|
||||
ok_r.bits.data := out.d.bits.data
|
||||
ok_r.bits.resp := d_resp
|
||||
ok_r.bits.last := d_last
|
||||
ok_r.bits.id := out.d.bits.source >> 1
|
||||
ok_r.bits.data := out.d.bits.data
|
||||
ok_r.bits.resp := d_resp
|
||||
ok_r.bits.last := d_last
|
||||
|
||||
r_err_out.ready := err_r.ready
|
||||
err_r.valid := r_err_out.valid
|
||||
err_r.bits.id := r_err_out.bits.id
|
||||
err_r.bits.data := out.d.bits.data // don't care
|
||||
err_r.bits.resp := AXI4Parameters.RESP_DECERR
|
||||
err_r.bits.last := r_err_out.bits.last
|
||||
r_err_out.ready := err_r.ready
|
||||
err_r.valid := r_err_out.valid
|
||||
err_r.bits.id := r_err_out.bits.id
|
||||
err_r.bits.data := out.d.bits.data // don't care
|
||||
err_r.bits.resp := AXI4Parameters.RESP_DECERR
|
||||
err_r.bits.last := r_err_out.bits.last
|
||||
|
||||
// AXI4 must hold R to one source until last
|
||||
val mux_lock_ok = RegInit(Bool(false))
|
||||
val mux_lock_err = RegInit(Bool(false))
|
||||
when (ok_r .fire()) { mux_lock_ok := !ok_r .bits.last }
|
||||
when (err_r.fire()) { mux_lock_err := !err_r.bits.last }
|
||||
assert (!mux_lock_ok || !mux_lock_err)
|
||||
// AXI4 must hold R to one source until last
|
||||
val mux_lock_ok = RegInit(Bool(false))
|
||||
val mux_lock_err = RegInit(Bool(false))
|
||||
when (ok_r .fire()) { mux_lock_ok := !ok_r .bits.last }
|
||||
when (err_r.fire()) { mux_lock_err := !err_r.bits.last }
|
||||
assert (!mux_lock_ok || !mux_lock_err)
|
||||
|
||||
// Prioritize err over ok (b/c err_r.valid comes from a register)
|
||||
mux_r.valid := (!mux_lock_err && ok_r.valid) || (!mux_lock_ok && err_r.valid)
|
||||
mux_r.bits := Mux(!mux_lock_ok && err_r.valid, err_r.bits, ok_r.bits)
|
||||
ok_r.ready := mux_r.ready && (mux_lock_ok || !err_r.valid)
|
||||
err_r.ready := mux_r.ready && !mux_lock_ok
|
||||
// Prioritize err over ok (b/c err_r.valid comes from a register)
|
||||
mux_r.valid := (!mux_lock_err && ok_r.valid) || (!mux_lock_ok && err_r.valid)
|
||||
mux_r.bits := Mux(!mux_lock_ok && err_r.valid, err_r.bits, ok_r.bits)
|
||||
ok_r.ready := mux_r.ready && (mux_lock_ok || !err_r.valid)
|
||||
err_r.ready := mux_r.ready && !mux_lock_ok
|
||||
|
||||
// AXI4 needs irrevocable behaviour
|
||||
in.r <> Queue.irrevocable(mux_r, 1, flow=true)
|
||||
// AXI4 needs irrevocable behaviour
|
||||
in.r <> Queue.irrevocable(mux_r, 1, flow=true)
|
||||
|
||||
ok_b.bits.id := out.d.bits.source >> 1
|
||||
ok_b.bits.resp := d_resp
|
||||
ok_b.bits.id := out.d.bits.source >> 1
|
||||
ok_b.bits.resp := d_resp
|
||||
|
||||
w_err_out.ready := err_b.ready
|
||||
err_b.valid := w_err_out.valid
|
||||
err_b.bits.id := w_err_out.bits
|
||||
err_b.bits.resp := AXI4Parameters.RESP_DECERR
|
||||
w_err_out.ready := err_b.ready
|
||||
err_b.valid := w_err_out.valid
|
||||
err_b.bits.id := w_err_out.bits
|
||||
err_b.bits.resp := AXI4Parameters.RESP_DECERR
|
||||
|
||||
// Prioritize err over ok (b/c err_b.valid comes from a register)
|
||||
mux_b.valid := ok_b.valid || err_b.valid
|
||||
mux_b.bits := Mux(err_b.valid, err_b.bits, ok_b.bits)
|
||||
ok_b.ready := mux_b.ready && !err_b.valid
|
||||
err_b.ready := mux_b.ready
|
||||
// Prioritize err over ok (b/c err_b.valid comes from a register)
|
||||
mux_b.valid := ok_b.valid || err_b.valid
|
||||
mux_b.bits := Mux(err_b.valid, err_b.bits, ok_b.bits)
|
||||
ok_b.ready := mux_b.ready && !err_b.valid
|
||||
err_b.ready := mux_b.ready
|
||||
|
||||
// AXI4 needs irrevocable behaviour
|
||||
in.b <> Queue.irrevocable(mux_b, 1, flow=true)
|
||||
// AXI4 needs irrevocable behaviour
|
||||
in.b <> Queue.irrevocable(mux_b, 1, flow=true)
|
||||
|
||||
// Update flight trackers
|
||||
val r_set = in.ar.fire().asUInt << in.ar.bits.id
|
||||
val r_clr = (in.r.fire() && in.r.bits.last).asUInt << in.r.bits.id
|
||||
r_inflight := (r_inflight | r_set) & ~r_clr
|
||||
val w_set = in.aw.fire().asUInt << in.aw.bits.id
|
||||
val w_clr = in.b.fire().asUInt << in.b.bits.id
|
||||
w_inflight := (w_inflight | w_set) & ~w_clr
|
||||
// Update flight trackers
|
||||
val r_set = in.ar.fire().asUInt << in.ar.bits.id
|
||||
val r_clr = (in.r.fire() && in.r.bits.last).asUInt << in.r.bits.id
|
||||
r_inflight := (r_inflight | r_set) & ~r_clr
|
||||
val w_set = in.aw.fire().asUInt << in.aw.bits.id
|
||||
val w_clr = in.b.fire().asUInt << in.b.bits.id
|
||||
w_inflight := (w_inflight | w_set) & ~w_clr
|
||||
|
||||
// Unused channels
|
||||
out.b.ready := Bool(true)
|
||||
out.c.valid := Bool(false)
|
||||
out.e.valid := Bool(false)
|
||||
// Unused channels
|
||||
out.b.ready := Bool(true)
|
||||
out.c.valid := Bool(false)
|
||||
out.e.valid := Bool(false)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user