riscv/rocket-chip
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use options for NastiWriteDataChannel write mask

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This commit is contained in:
Howard Mao 2016-07-05 16:03:25 -07:00
parent ed9fcea7f8
commit 96f09003f2
2 changed files with 4 additions and 9 deletions
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2
junctions/src/main/scala/atos.scala
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@ -246,7 +246,7 @@ class AtosRequestDecoder(implicit p: Parameters) extends AtosModule()(p) {
io.w.bits := NastiWriteDataChannel( io.w.bits := NastiWriteDataChannel(
id = io.req.bits.id(), id = io.req.bits.id(),
data = io.req.bits.data(), data = io.req.bits.data(),
strb = io.req.bits.strb(), strb = Some(io.req.bits.strb()),
last = io.req.bits.last()) last = io.req.bits.last())
io.req.ready := (io.ar.ready && is_ar) || io.req.ready := (io.ar.ready && is_ar) ||

11
junctions/src/main/scala/nasti.scala
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@ -168,21 +168,16 @@ object NastiReadAddressChannel {
} }
object NastiWriteDataChannel { object NastiWriteDataChannel {
def apply(data: UInt, last: Bool = Bool(true), id: UInt = UInt(0)) def apply(data: UInt, strb: Option[UInt] = None,
last: Bool = Bool(true), id: UInt = UInt(0))
(implicit p: Parameters): NastiWriteDataChannel = { (implicit p: Parameters): NastiWriteDataChannel = {
val w = Wire(new NastiWriteDataChannel) val w = Wire(new NastiWriteDataChannel)
w.strb := Fill(w.nastiWStrobeBits, UInt(1, 1)) w.strb := strb.getOrElse(Fill(w.nastiWStrobeBits, UInt(1, 1)))
w.data := data w.data := data
w.last := last w.last := last
w.user := UInt(0) w.user := UInt(0)
w w
} }
def apply(data: UInt, strb: UInt, last: Bool, id: UInt)
(implicit p: Parameters): NastiWriteDataChannel = {
val w = apply(data, last, id)
w.strb := strb
w
}
} }
object NastiReadDataChannel { object NastiReadDataChannel {