riscv/rocket-chip
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pass parameters to BuildRoCC

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This commit is contained in:
Henry Cook 2015-10-14 14:16:47 -07:00
parent 68cb54bc68
commit 969ecaecf8
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/tile.scala
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@ -9,7 +9,7 @@ import Util._
case object CoreName extends Field[String] case object CoreName extends Field[String]
case object NDCachePorts extends Field[Int] case object NDCachePorts extends Field[Int]
case object NPTWPorts extends Field[Int] case object NPTWPorts extends Field[Int]
case object BuildRoCC extends Field[Option[() => RoCC]] case object BuildRoCC extends Field[Option[Parameters => RoCC]]
abstract class Tile(resetSignal: Bool = null) abstract class Tile(resetSignal: Bool = null)
(implicit p: Parameters) extends Module(_reset = resetSignal) { (implicit p: Parameters) extends Module(_reset = resetSignal) {
@ -51,7 +51,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
// If so specified, build an RoCC module and wire it in // If so specified, build an RoCC module and wire it in
// otherwise, just hookup the icache // otherwise, just hookup the icache
io.uncached <> p(BuildRoCC).map { buildItHere => io.uncached <> p(BuildRoCC).map { buildItHere =>
val rocc = buildItHere() val rocc = buildItHere(p)
val memArb = Module(new ClientTileLinkIOArbiter(3)) val memArb = Module(new ClientTileLinkIOArbiter(3))
val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams)) val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
core.io.rocc <> rocc.io core.io.rocc <> rocc.io